4

Integrated

Circuit

Systems, Inc.

ICS9FG1901

0962E—01/02/07

Block Diagram

Power Groups

The ICS9FG1901 follows the Intel DB1900G Differential Buffer Specification. This buffer provides 19 output clocks for CPU Host

Bus, PCI-Express, or Fully Buffered DIMM applications. The outputs are configured with two groups. Both groups, DIF_(16:0) and

DIF_(18:17) can be equal to or have a gear ratio to the input clock. A differential CPU clock from a CK410 or CK410B main clock

generator, such as the ICS954101 or ICS932S401, drives the ICS9FG1901. The ICS9FG1901 can provide outputs up to

400MHz.

General Description

STOP

LOGIC

CLK_IN

CLK_IN#

DIF(16:0)

CONTROL

LOGIC

HIGH_BW#

SMB_A2_PLLBYP#

SMBDAT

SMBCLK

SPREAD

COMPATIBLE

PLL

17

IREF

OE(16:5)#,

OE_01234#

13

SMB_A0

SMB_A1

FS_A_410

STOP

LOGIC

DIF(18:17)

2

OE_17_18#

GEAR

SHIFT

LOGIC

SPREAD

COMPATIBLE

PLL

GEAR

SHIFT

LOGIC

VDD

GND

3

2

Main PLL, Analog

11,27,47,63 10,28,46,64

DIF clocks

Description

Pin Number