8

Integrated

Circuit

Systems, Inc.

ICS9FG1901

0962E—01/02/07

PLL Bandwidth and Peaking

Parameter

Conditions

Min

Typical

Max

Units

Notes

PLL Jitter Peaking

jpeak-hibw

(HIGH_BW# = 0)

0

1

2.5

dB

2,8

PLL Jitter Peaking

jpeak-lobw

(HIGH_BW# = 1)

0

1

2

dB

2,8

PLL Bandwidth

pllHIBW

(HIGH_BW# = 0)

2

2.3

4

MHz

1,8

PLL Bandwidth

pllLOBW

(HIGH_BW# = 1)

0.7

1.28

1.4

MHz

1,8

Output phase jitter impact – PCIe*

Gen1

θPCIe1

(including PLL BW 1.5-22 MHz, z = 0.54,

Td=10 ns, Ftrk=1.5 MHz )

0

77

108

ps

3,6,7,8

Output phase jitter impact – FBD

θFBD

(including PLL BW 11- 33 Mz, z = 0.54,

Td=5 ns, Ftrk=0.2 MHz)

0

3

ps RMS 3,4,7,8

NOTES:

1.

Measured at 3 db down or half power point.

2.

Measured as maximum pass band gain. At frequencies within the loop BW, highest point of magnification is called PLL jitter peaking.

3.

Post processed evaluation through Intel supplied Matlab scripts.

4.

Refer to FB-DIMM Specification: “High Speed Differential Point-to-Point Link at 1.5 V” for updates to this specification.

6.

These jitter numbers are defined for a BER of 1E-12. Measured numbers at a smaller sample size have to be extrapolated to this BER target.

7.

z

= 0.54 is implying a jitter peaking of 3 dB.

8. Guaranteed by design and characterization, not 100% tested in production.

5.

PCIe* Gen2 filter characteristics are subject to final ratification by PC ISIG. Please check the PCI* SIG for the latest specification. Tested with DBxx00G driven by low phase

noise signal generator such as an Agilent 8133A.