Integrated

Circuit

Systems, Inc.

ICS9FG1901

0962E—01/02/07

Recommended Application:

DB1900G: CPU Host Bus, PCI Express and Fully-Buffered

DIMM clocking

Features:

•

Power up default is all outputs in 1:1 mode

•

DIF_(16:0) can be “gear-shifted” from the input CPU

Host Clock

•

DIF_(18:17) can be “gear-shifted” from the input CPU

Host Clock

•

Spread spectrum compatible

•

Supports output clock frequencies up to 400 MHz

•

8 Selectable SMBus addresses

•

SMBus address determines PLL or Bypass mode

•

VDDA controlled power down mode

Key Specifications:

•

DIF output cycle-to-cycle jitter < 50ps

•

DIF (0:18) output-to-output skew < 225ps

•

DIF (0:16) output-to-output skew < 100ps

Frequency Generator for P4™

™

™

™

™ CPU, PCI Express™™™™™ & Fully Buffered DIMM Clocks

Other names and brands may be claimed as the property of others.

Power Down Functionality

Pin Configuration

72-pin MLF

Functionality at Power Up (PLL Mode)

72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55

IREF

1

54 OE14#

GNDA

2

53 DIF_13#

VDDA/PD#

3

52 DIF_13

HIGH_BW#

4

51 OE13#

FS_A_410

5

50 DIF_12#

DIF_0

6

49 DIF_12

DIF_0#

7

48 OE12#

DIF_1

8

47 VDD

DIF_1#

9

46 GND

GND 10

45 DIF_11#

VDD 11

44 DIF_11

DIF_2 12

43 OE11#

DIF_2# 13

42 DIF_10#

DIF_3 14

41 DIF_10

DIF_3# 15

40 OE10#

DIF_4 16

39 DIF_9#

DIF_4# 17

38 DIF_9

OE_01234# 18

37 OE9#

19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

ICS9FG1901

FS_A_410

1

CLK_IN (CPU FSB)

MHz

DIF_(18:0)

MHz

1

100 <= CLK_IN < 200

CLK_IN

0

200<= CLK_IN <= 400

CLK_IN

1. FS_A_410 is a low-threshold input. Please see the VIL_FS and VIH_FS

specifications in the Input/Supply/Common Output Parameters Table for

correct values.

VDDA/PD#

CLK_IN/CLK_IN#

DIF

DIF#

3.3V (NOM)

Running

ON

GND

X

OFF

Functionality Note

It is recommended that Byte 2, bit 6 be toggled from 1 to 0

and back to 1, the first time VDDA is applied. This ensures

proper initialization of the device.

Hi-Z

INPUTS

OUTPUTS

PLL State

Running