MPC7448 datasheet(15/60 Pages) FREESCALE

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MPC7448 RISC Microprocessor Hardware Specifications, Rev. 3

Freescale Semiconductor

Electrical and Thermal Characteristics

5.2

AC Electrical Characteristics

This section provides the AC electrical characteristics for the MPC7448. After fabrication, functional parts

are sorted by maximum processor core frequency as shown in Section 5.2.1, “Clock AC Specifications,”

and tested for conformance to the AC specifications for that frequency. The processor core frequency,

determined by the bus (SYSCLK) frequency and the settings of the PLL_CFG[0:5] signals, can be

dynamically modified using dynamic frequency switching (DFS). Parts are sold by maximum processor

core frequency; see Section 11, “Part Numbering and Marking,” for information on ordering parts. DFS is

described in Section 9.7.5, “Dynamic Frequency Switching (DFS).”

5.2.1

Clock AC Specifications

Table 8 provides the clock AC timing specifications as defined in Figure 3 and represents the tested

operating frequencies of the devices. The maximum system bus frequency, fSYSCLK, given in Table 8, is

considered a practical maximum in a typical single-processor system. This does not exclude

multi-processor systems, but these typically require considerably more design effort to achieve the

maximum rated bus frequency. The actual maximum SYSCLK frequency for any application of the

MPC7448 will be a function of the AC timings of the microprocessor(s), the AC timings for the system

controller, bus loading, circuit board topology, trace lengths, and so forth, and may be less than the value

given in Table 8.

Table 8. Clock AC Timing Specifications

At recommended operating conditions. See Table 4.

Characteristic

Symbol

Maximum Processor Core Frequency (Speed Grade)

Unit

Notes

1000 MHz

1420 MHz

1600 MHz

1700 MHz

Min

Max

Min

Max

Min

Max

Min

Max

Processor

core

frequency

DFS mode disabled

fcore

600

1000

600

1420

600

1600

600

1700

MHz

1, 8

DFS mode enabled

fcore_DF

300

500

300

710

300

800

300

850

VCO frequency

fVCO

600

1000

600

1420

600

800

600

1700

MHz

1, 10

SYSCLK frequency

fSYSCLK

200

MHz

1, 2, 8

SYSCLK cycle time

tSYSCLK

5.0

SYSCLK rise and fall time

tKR, tKF

—0.5

SYSCLK duty cycle measured at

OVDD/2

tKHKL/

tSYSCLK

SYSCLK cycle-to-cycle jitter

—

150

—

150

—

150

—

150

5, 6

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