THS8083CPZP datasheet(42/61 Pages) TI

Part #	THS8083CPZP

Description	Triple 8-Bit, 80 MSPS, 3.3-V Video and Graphics Digitizer With Digital PLL

PDF	61 Pages

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Manufacturer	TI [Texas Instruments]

Direct Link	http://www.ti.com

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42 / 61 page

4–2

4.2

Timing Diagram – 16-Bit Parallel Mode

This is the ITU.BT–601 style mode that will typically be used in YUV operation of the part with a Y analog input

connected to the Ch1 input of THS8083, Cb from Ch.2 input, and Cr from Ch.3 input. The DATACLK1 output is at

the sampling clock frequency and Ch3 remains unused. Output bus B of all channels is high impedance. The DHS

signal can be used to uniquely identify Cb from Cr output data.

DATACLK

CH1_OUTA[7..0]

CH2_OUTA[7..0]

CH2_OUTB[7..0]

CH1_OUTB[7..0]

CH3_OUTA[7..0]

CH3_OUTB[7..0]

DHS

Cb: From Ch.2 Input

Cr: From Ch.3 Input

pix 01

pix 02

ADCCLK2

tPLH(OE)

tPHL(OE)

tsu(OUT)

th(OUT)

th(DHS)

tsu(DHS)

<DHS_MODE> = 1 –> Width

Equal to Width of HS Input

<DHS_MODE> = 0 –> DHS

Width is 1 ADCCLK2 Period

7 ADCCLK2

Cycles Latency

(DHS_POL = 0

Assumed-Inverted

Polarity Otherwise)

7 ADCCLK2 Cycles Latency

Last Samples From Previous Line

01(Cr)

01(Cb)

03(Cb)

Last Samples From Previous Line

THS8083CPZP Datasheet(PDF) 42 Page - Texas Instruments

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