THS8083CPZP datasheet(18/61 Pages) TI

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2–4

2.4

Programmable Gain Amplifier (PGA)

Each video channel is passed through a programmable gain amplifier, to provide a full-scale signal to each A/D. The

user can change this gain via register programming. A gain change becomes effective immediately.

The range of the PGA is such that an input ac range from 0.4 Vpp to 1.2 Vpp can be scaled to ADC full scale, by

maximum gain and minimum gain settings respectively.

The PGA is split into a 6-bit coarse gain control and 5-bit fine gain control. Their combination leads to a PGA resolution

of better than 1 LSB on the ADC output code.

The bandwidth of the PGA is by design constant, resulting in a constant analog video input bandwidth.

The coarse PGA, with its 64 settings, covers a 4/3 x to 4x gain change, used for a 0.4 V (0.4 Vpp

× 4 = 1.6 Vpp)

respectively 1.2 Vpp (1.2 Vpp

× 4/3 = 1.6 Vpp) input range swing.

While an amplifier with variable gain implements the coarse PGA, the fine PGA is implemented by slightly changing

the top and bottom reference levels that are also independently controllable for each ADC channel. The fine range,

with its 32 settings, covers a range of 16 LSBs.

The fine and coarse PGA settings can be combined into a single PGA gain formula as follows:

GAIN = (4/3 + C/24)(1 + (F–15)/512)

Where C is the coarse gain setting (0..63) and F the fine gain setting (0..31).

2.5

A/D Converter

The A/D converter is based on the core used in the TLV5580 (single 8-bit 80 MSPS A/D). The switched-capacitor

single-pipeline CMOS architecture combines excellent signal-to-noise characteristics with a very wide 3-dB analog

input bandwidth of typically 500 MHz. The A/D block contains an internal reference voltage generator, providing stable

bottom and top references derived from an internal bandgap reference. The reference voltages are made available

externally. The THS8083 supports ac-coupled input (clamping circuit).

The A/D converter will have no missing codes up to 80 MSPS if used as defined in section 5, Electrical Specification.

The sampling clock of the A/D converter is either fed from external or generated internally by the PLL.

2.6

PLL

The PLL is a fully contained functional block consisting of:

•

An analog PLL operating at a fixed output frequency of N times the master (crystal) clock frequency

•

A digital PLL containing a digital phase-frequency detector (PFD), a discrete time oscillator (DTO), a digital

loop filter, a feedback divider, a programmable clock output divider, and a programmable phase shifter

2.6.1

Analog PLL

The analog PLL generates a high-frequency internal clock that will be used by the DTO in the digital PLL to derive

the pixel output frequency with programmable phase. The reference signal for this PLL is the master clock frequency

supplied on the XTL1-MCLK terminal.

Two options exist for connecting a master clock:

•

A crystal can be connected between the XTL1-MCLK and XTL2 terminals. The device provides internal

oscillator circuitry.

•

A 3.3-V CMOS/TTL clock signal can be connected to XTL1-MCLK from an external oscillator. In this case

XTL2 must be left unconnected.

THS8083CPZP Datasheet(PDF) 18 Page - Texas Instruments

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