CYT4DNJBJS datasheet(111/209 Pages) INFINEON

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Datasheet

111

002-24601 Rev. *I

2023-02-14

TRAVEO™ T2G 32-bit Automotive MCU

Based on Arm® Cortex®-M7 dual

Electrical specifications

SID661 VIH_TTL

Input voltage HIGH

threshold in TTL

mode

2.0

–

CFG_IN_AU-

TOLVL/VTRIP_SEL<0:0> = 0b0

CFG_IN/VTRIP_SEL<0:0> = 0b1

SID662 VIH_AUTO

Input voltage HIGH

threshold in AUTO

mode

0.8 ×

VDDIO_GPIO

––

CFG_IN_AU-

TOLVL/VTRIP_SEL<0:0> = 0b1

CFG_IN/VTRIP_SEL<0:0> = 0b0

4.5 V  VDDIO_GPIO  5.5 V

SID663 VIL_CMOS

Input voltage LOW

threshold in CMOS

mode

–

0.3 ×

DDIO_GPIO

CFG_IN_AU-

TOLVL/VTRIP_SEL<0:0> = 0b0

CFG_IN/VTRIP_SEL<0:0> = 0b0

SID664 VIL_TTL

Input voltage LOW

threshold in TTL

mode

––

0.8

CFG_IN_AU-

TOLVL/VTRIP_SEL<0:0> = 0b0

CFG_IN/VTRIP_SEL<0:0> = 0b1

SID665 VIL_AUTO

Input voltage LOW

threshold in AUTO

mode

–

0.5 ×

DDIO_GPIO

CFG_IN_AU-

TOLVL/VTRIP_SEL<0:0> = 0b1

CFG_IN/VTRIP_SEL<0:0> = 0b0

4.5 V  VDDIO_GPIO  5.5 V

SID666 VHYST_CMOS Hysteresis in CMOS

mode

0.05 ×

DDIO_GPIO

––

CFG_IN_AU-

TOLVL/VTRIP_SEL<0:0> = 0b0

CFG_IN/VTRIP_SEL<0:0> = 0b0

SID668 VHYST_AUTO Hysteresis in AUTO

mode

0.05 ×

DDIO_GPIO

––

CFG_IN_AU-

TOLVL/VTRIP_SEL<0:0> = 0b1

CFG_IN/VTRIP_SEL<0:0> = 0b0

4.5 V  VDDIO_GPIO  5.5 V

SID669 CIN

Input pin capaci-

tance

––

pF Test condition: 10/100MHz

SID670 IIL

Input leakage current

–1

–

µA VDDIO_GPIO = VDDD = 5.5 V,

VSS < VI < VDDIO_GPIO_x

-40 °C ≤ TA ≤ 105 °C

This is valid for the pin which do

not have ADC input functionality.

SID671 tR_F_FAST

Rise time or fall time

(10% to 90% of

DDIO_GPIO)

1–

ns CFG_OUT/DRIVE_SEL<1:0> =

0b00, 20-pF load,

entire VDDIO_GPIO range

SID672 tR_F_FAST

Rise time or fall time

(10% to 90% of

DDIO_GPIO)

1–

ns CFG_OUT/DRIVE_SEL<1:0> =

0b00, 50-pF load, entire

VDDIO_GPIO range, Guaranteed by

design

SID673 tR_F_FAST

Rise time or fall time

(10% to 90% of

DDIO_GPIO)

1–

ns CFG_OUT/DRIVE_SEL<1:0> =

0b01, 20-pF load, entire

VDDIO_GPIO range, Guaranteed by

design

SID674 tR_F_FAST

Rise time or fall time

(10% to 90% of

DDIO_GPIO)

1–

ns CFG_OUT/DRIVE_SEL<1:0> =

0b10, 10-pF load, entire

VDDIO_GPIO range, Guaranteed by

design

SID675 tR_F_FAST

Rise time or fall time

(10% to 90% of

DDIO_GPIO)

1–

ns CFG_OUT/DRIVE_SEL<1:0> =

0b11, 6-pF load, entire VDDIO_GPIO

range, Guaranteed by design

GPIO_SMC specifications (Stepper Motor Control, 5-V I/Os)

SID650A VOL2

Output voltage LOW

level

––

0.6

IOL = 6 mA

CFG_OUT/DRIVE_SEL<1:0> =

0b01

VDDIO_SMC ≥ 4.5 V

SID651A VOL2

Output voltage LOW

level

––

0.4

IOL = 5 mA

CFG_OUT/DRIVE_SEL<1:0> =

0b01

VDDIO_SMC ≥ 4.5 V

SID651E VOL2

Output voltage LOW

level

––

0.4

IOL = 2 mA

CFG_OUT/DRIVE_SEL<1:0> =

0b01

2.7 V  VDDIO_SMC < 4.5 V

Table 26-5

I/O specifications (continued)

Spec ID Parameter

Description

Min

Typ

Max

Units

Details/conditions

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