CYT4DNJBJS datasheet(179/209 Pages) INFINEON

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Datasheet

179

002-24601 Rev. *I

2023-02-14

TRAVEO™ T2G 32-bit Automotive MCU

Based on Arm® Cortex®-M7 dual

Electrical specifications

Figure 26-6

SDR write and read timing diagram

Figure 26-7

DDR write and read timing diagram

Note

88.For other frequencies: tOSU = (13/16 × tDLL) – 0.3 ns, tDLL is the clock period of the input clock of the DLL.

89.For other frequencies: tOH = (13/16 × tDLL) – 0.3 ns, tDLL is the clock period of the input clock of the DLL.

90.For tOH timing between 80 MHz and 100 MHz, use following formula: tOH = 2.8 - 0.015 × fCK, where fCK is the memory clock frequency

in MHz, and tOH is hold time in ns.

1: CS# active setup to CK = tCSS

2: Data setup time = tISU*

3: Data hold time = tIH*

4: CK low to DQ[7:0] input valid time = tIN_V

5: Read data valid time of DQ[7:0] = tRDV

6: Output setup of DQ[7:0] to CK rise = tOSU

7: Output hold time of DQ[7:0] from CK rise = tOH

8: CS# active hold to CK = tCSH

9: CS# inactive to output disable = tDIS

10: Chip select HIGH time = tCS

*Note: Reference is CK falling edge for the pos capture mode

Chip

select

Data

LSB OUT

MSB OUT

Read timing

Write timing

MSB IN

LSB IN

Chip

select

Data

MSB IN

LSB IN

MSB IN

LSB IN

1: CS# active setup to CK = tCSS

2: CK edge to DQ[7:0] input valid time = tIN_V

3: Read data valid time of DQ[7:0] = tRDV

4: Output setup of DQ[7:0] to CK edge = tOSU

5 Output hold time of DQ[7:0] from CK edge = tOH

6: CS# active hold to CK = tCSH

7: Chip select HIGH time = tCS

8: CS# inactive to output disable = tDIS

Read timing

Write timing

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