CYT4DNJBJS datasheet(181/209 Pages) INFINEON

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Datasheet

181

002-24601 Rev. *I

2023-02-14

TRAVEO™ T2G 32-bit Automotive MCU

Based on Arm® Cortex®-M7 dual

Electrical specifications

SID885_1 IVDDPLL_PD_1

Total PLL supply current in

Power-Down mode (room temp)

–

µA

Max: TA=25°C,VDDPLL_FPD=

1.15 V (max VREG), process

worst (FF)

SID885_2 IVDDPLL_PD_2

Total PLL supply current in

Power-Down mode

–

µA

Max: TA=85°C,VDDPLL_FPD=

1.15 V (max VREG), process

worst (FF)

SID885B

IVDDHA_PD

Total I/O (LVDS driver) supply

current in Power-Down mode

–

0.5

µA

Typ: TA = 25°C, VDDHA_FPD =

3.3 V, process typ (TT)

Max: TA = 105°C, VDDHA_FPD

= 3.6 V, process worst (FF)

SID885B_1 IVDDHA_PD_1

Total I/O (LVDS driver) supply

current in Power-Down mode

(room temp)

–

µA

Max: TA = 25°C, VDDHA_FPD =

3.6 V (max VREG),

process worst (FF)

SID885B_2 IVDDHA_PD_2

Total I/O (LVDS driver) supply

current in Power-Down mode

–

µA

Max: TA = 85°C, VDDHA_FPD =

3.6 V (max VREG),

process worst (FF)

SID895

VOD

Steady-state magnitude of the

differential output voltage

247

350

454

SID896

VΔVOD_M

Variation of signal swing voltage

between drivers

–

SID897

VCM

Output Common-mode voltage

1.125

1.25

1.375

SID898

VΔVCM_M

Delta in Common-mode voltage

between drivers

–

SID899A

ISA

Magnitude of current flowing

through output terminal P when

the output terminals are

short-circuited to ground.

–

See Figure 6 of

“TIA/EIA-644-A”

specifications.

SID899B

ISB

Magnitude of current flowing

through output terminal M when

the output terminals are

short-circuited to ground.

–

See Figure 6 of

“TIA/EIA-644-A”

specifications.

SID899C

IOS

Magnitude of current flowing

through theoutput terminals when

they are short-circuited to each

other.

–

See Figure 7 of

“TIA/EIA-644-A”

specifications.

SID900

tWAKE

Wakeup time

–

1.2

SID901

tPDD

Power down delay time

–

100

µs

Guaranteed by design

SID902

fPX

Pixel Clock Frequency

–

110

MHz Guaranteed by design

SID903

fPX110

Output Clock Frequency (110 MHz)

103.7

110

116.3

MHz When transmitting an

alternating 0/1 bit pattern

SID904

fPX55

Output Clock Frequency (55 MHz)

52.35

57.65

MHz When transmitting an

alternating 0/1 bit pattern

SID905

fPX28

Output Clock Frequency (28 MHz)

26.66

29.34

MHz When transmitting an

alternating 0/1 bit pattern

SID906

fPX14

Output Clock Frequency (14 MHz)

13.28

14.72

MHz When transmitting an

alternating 0/1 bit pattern

SID907

fPX7

Output Clock Frequency (7 MHz)

6.59

7.41

MHz When transmitting an

alternating 0/1 bit pattern

SID908

GAIN_JIT_LVDS

Gain region max long-term total

jitter

–

0.32

UI2 p-p

SID909

ATTEN_JIT_LVDS

Attenuation region long-term total

jitter

–

0.34

UI2 p-p

SID910

C2C_JIT

Cycle-to-cycle jitter

–

0.11

SID911

tCSK

Channel-to-channel skew of driver

outputs

–

100

SID913

TPPos0

Transmit Pulse Position Offset 0

–0.168

0.168

SID914

TPPos1

Transmit Pulse Position Offset 1

T / 7 –

TPPos0

T / 7

T / 7 +

TPPos0

SID915

TPPos2

Transmit Pulse Position Offset 2

2T / 7 –

TPPos0

2T / 7

T / 7 +

TPPos0

Table 26-39

Graphics specifications (continued)

Spec ID

Parameter

Description

Min

Typ

Max

Units

Details/Conditions

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