ICS580-01

GLITCH-FREE CLOCK MULITPLEXER

CLOCK MULTIPLEXER

IDT™ / ICS™ GLITCH-FREE CLOCK MULITPLEXER

4

ICS580-01

REV L 051310

Device Operation

The ICS580-01 consists of a glitch free mux between INA and INB controlled by SELB. The device is designed to

switch between two clocks, whether running or not. In the first example, clocks are running on both INA and INB.

When SELB changes, the output clock goes low after three cycles of the output clock (nominally). The output then

stays low for three cycles of the new input clock (nominally) and then starts with the new input clock. This is shown

in Figure 1.

In the second example, one of the inputs was selected and running but has since stopped (either high or low). This

is indicated by either NO_INA or NO_INB going high depending on whether INA or INB has stopped. These signals

go high following a selectable time-out period after the clock has stopped. The timeout period is determined by the

DIV input in. The SELB pin is now changed to select the new input clock which is running. The output clock

immediately goes low and stays low for three cycles of the new input clock and then starts with the new input clock.

Figure 2 shows an example of this

INA

INB

SELB

CLK1, 2

Figure 1

INA

INB

SELB

NO_INA

Figure 2

Timeout

CLK1, 2