ICS1894-44 datasheet(39/54 Pages) RENESAS

Part #	ICS1894-44

Description	10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH MII INTERFACE

PDF	54 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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ICS1894-44

10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH MII INTERFACE

PHYCEIVER

IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH MII INTERFACE

ICS1894-44

REV B 030112

100M / MII Media Independent Interface: Transmit Latency

The table below lists the significant time periods for the MII/100 Stream Interface transmit latency. The time periods

consist of timings of signals on the following pins:

• TXEN

• TXCLK

• TXD (that is, TXD[3:0])

• TP_TX (that is, TP_TXP and TP_TXN)

The MII/100M Stream Interface Transmit Latency Timing Diagram shows the timing diagram for the time periods.

†The IEEE maximum is 18 bit times.

MII/100M Stream Interface Transmit Latency Timing Diagram

Time

Period

Parameter

Conditions

Min. Typ.

Max.

Units

TXEN Sampled to MDI Output of First

Bit of /J/ †

MII mode

–

2.8

Bit times

TXEN

TXCLK

TXD

TP_TX†

† Shown

unscrambled.

Preamble /K/

Preamble /J/

ICS1894-44 Datasheet(PDF) 39 Page - Renesas Technology Corp