ICS1894-44 datasheet(14/54 Pages) RENESAS

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ICS1894-44

10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH MII INTERFACE

PHYCEIVER

IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH MII INTERFACE

ICS1894-44

REV B 030112

Pins for Monitoring the Data Link table

Note:

1. During either power-on reset or hardware reset, each

multi-function configuration pin is an input that is sampled

when the ICS1894-44 exits the reset state. After sampling is

complete, these pins are output pins that can drive status

LEDs.

2. A software reset does not affect the state of a

multi-function configuration pin. During a software reset, all

multi-function configuration pins are outputs.

3. The P0/LED0 and P1/ISO/LED1 pins must be pulled

either up or down with an external resistor to establish the

address of the ICS1894-44. The P2/INT, P3/RXD2 and

P4/LED2 pins have internal pull-up/ pull-down resistors.

LEDs may be placed in series with these resistors to provide

a designated status indicator as described in the Pins for

Monitoring the Data Link table. Use 1K

Ω resistors.

Caution: Pins listed in the Pins for Monitoring the Data Link

table must not float.

4. As outputs, the asserted state of a multi-function

configuration pin is the inverse of the sense sampled during

reset. This inversion provides a signal that can illuminate an

LED during an asserted state. For example, if a

multi-function configuration pin is pulled down to ground

through an LED and a current-limiting resistor, then the

sampled sense of the input is low. To illuminate this LED for

the asserted state, the output is driven high.

5. Adding 10K

Ωresistors across the LEDs ensures the PHY

address is fully defined during slow VDD power-ramp

conditions.

The following figure shows typical biasing and LED connections for the ICS1894-44.

The above circuit decodes the PHY address = 17

LED Driven by the Pin’s Output Signal

P0/LED0