TMPR4955AF datasheet(132/168 Pages) TOSHIBA

132 / 168 page

Chapter 6 TX4955A System Interface

6-60

6.3.19

Physical Addresses

Physical addresses are driven on all 32 bits (bits 31 through 0) of the SysAD bus during

address cycles. Addresses associated with single read and write requests are aligned for the

size of the data element; specifically, for single word requests, the low order two bits of the

address are zero, for halfword requests, the low order bit of the address is zero. For byte

and tribyte requests, the address provided is a byte address.

External agents returning read response data must support subblock ordering.

Addresses associated with block read requests are aligned to the word of the desired data.

The order in which data is returned in response to a processor block read request is:

•

the word containing the addressed data word is returned first

•

the remaining word(s) in the block are returned next, sequentially

Block writes are always block aligned

6.3.20

Mode Register of System Interface (G2SConfig)

The Mode Register of System Interface (G2SCofig) is a read/write register.

This register extend from TX4300.

This register is only WORD-Access.

Table 6.3.9 G2SConfig

Address

Field

Desctiption

0xF_FF10_0000

G2SConfig

Mode Register of System Interface

Reserved=0

TOutVal

TOut Enable

Reserved=0

BURST8

WBRATE

Figure 6.3.32 G2SConfig Register Format

Table 6.3.10 G2SConfig Register Formats (MODE43* = 0)

Bit

Field

Description

ColdReset

read/write

~20



Reserved

Undefined

read

TOutVal

Set Data of Read Time Out Counter

0xFFFF

read/write

TOutEnable

Enable bit of Read Time Out Counter

0: Disable

1: Enable

read/write



Reserved

Undefined

BURST8

Data Formats at 8-word burst write

0: Double burst mode 4 words

× 2

1: Single burst mode 8 words

read/write

WBRATE

Set bit of Data Out Formats

0: Every cycle Data Out

1: 4-word Data Out per 12 cycles

read/write

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