ICS843404 datasheet(12/20 Pages) RENESAS

12 / 20 page

843404AG

www.icst.com/products/hiperclocks.html

REV. A OCTOBER 17, 2005

Integrated

Circuit

Systems, Inc.

ICS843404

LVCMOS/CRYSTAL-TO-3.3V LVPECL AND

LVDS CLOCK GENERATOR

TERMINATION FOR 3.3V LVPECL OUTPUT

CC - 2V

RTT

o = 50Ω

FOUT

FIN

RTT =

((V

OH + VOL) / (VCC – 2)) – 2

3.3V

125

o = 50Ω

FOUT

FIN

The clock layout topology shown below is a typical termi-

nation for LVPECL outputs. The two different layouts men-

tioned are recommended only as guidelines.

FOUT and nFOUT are low impedance follower outputs that

generate ECL/LVPECL compatible outputs. Therefore, ter-

minating resistors (DC current path to ground) or current

sources must be used for functionality. These outputs are

FIGURE 4B. LVPECL OUTPUT TERMINATION

FIGURE 4A. LVPECL OUTPUT TERMINATION

designed to drive 50

Ω transmission lines. Matched imped-

ance techniques should be used to maximize operating

frequency and minimize signal distortion. Figures 4A and

4B show two different layouts which are recommended

only as guidelines. Other suitable clock layouts may exist

and it would be recommended that the board designers

simulate to guarantee compatibility across all printed cir-

cuit and clock component process variations.

ICS843404

LVCMOS/CRYSTAL-TO-3.3V LVPECL AND LVDS CLOCK GENERATOR

TSD

IDT™ / ICS™ LVCMOS/CRYSTAL-TO-3.3V LVPECL AND LVDS CLOCK GENERATOR

ICS843404

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