LP5860RKPR datasheet(22/71 Pages) TI

22 / 71 page

reading several consecutive registers within one transmission. If not consecutive, a new transmission must be

started.

Table 8-7. SPI Data Format

Address

Byte 1

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

9th bit

8th bit

7th bit

6th bit

5th bit

4th bit

3th bit

2th bit

Address

Byte 2

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

1th bit

0th bit

R: 0 W: 1

Don't Care

SCLK

MISO

MOSI

High Impedance

Address Byte 1

Address Byte 2

Data Byte 1

Data Byte 2

Figure 8-14. SPI Write Timing

SCLK

MISO

MOSI

High Impedance

Address Byte 1

Address Byte 2

Data Byte 1

Data Byte 2

Figure 8-15. SPI Read Timing

Multiple Devices Connection

The device enters into SPI mode if IFS is pulled high to VIO through a pullup resistor (4.7K Ω recommended).

VIO_EN can either be connected with VIO power supply or GPIO. TI suggests to put one 1-nF cap as closer to

VIO_EN pin as possible. In SPI mode host can address as many devices as there are follower select pins on

host.

LP5861T

SNVSCE4 – MAY 2023

www.ti.com

Submit Document Feedback

Product Folder Links: LP5861T

LP5860RKPR Datasheet(PDF) 22 Page - Texas Instruments

LP5860RKPR Datasheet(HTML) 22 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71

Datasheet Download

Link URL