ICS8714008I datasheet(3/35 Pages) RENESAS

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ICS8714008I DATA SHEET

FEMTOCLOCK® ZERO DELAY BUFFER/CLOCK GENERATOR FOR PCI EXPRESSTM AND ETHERNET

ICS8714008DKI REVISION A NOVEMBER 25, 2013

Pin Description and Pin Characteristic Tables

Table 1. Pin Descriptions

Number

Name

Type

Description

1, 7, 30, 37,

42, 45

VDD

Power

Core supply pins.

OE_MLVDS

Input

Pullup

Active High Output Enable. When HIGH, the M-LVDS output driver is active

and provides a buffered copy of reference clock applied the CLK, nCLK

input to the MLVDS, nMLVDS output pins. The MLVDS, nMLVDS

frequency equals the CLK, nCLK frequency divided by the PDIV Divider

value (selectable ÷1, ÷4, ÷5, ÷8). When LOW, the M-LVDS output driver is

placed into a High-impedance state and the MLVDS, nMLVDS pins can

accept a differential input. LVCMOS/LVTTL interface levels.

3MLVDS

I/O

Non-Inverting M-LVDS input/output. The input/output state is determined by

the OE_MLVDS pin. When OE_MLVDS = HIGH, this pin is an output and

drives the non-inverting M-LVDS output. When OE_MLVDS = LOW, this pin

is an input and can accept the following differential input levels: M-LVDS,

LVDS, LVPECL, HSTL, HCSL.

4nMLVDS

I/O

Inverting M-LVDS input/output. The input/output state is determined by the

OE_MLVDS pin. When OE_MLVDS = HIGH, this pin is an output and drives

the inverting M-LVDS output. When OE_MLVDS = LOW, this pin is an input

and can accept the following differential input levels: M-LVDS, LVDS,

LVPECL, HSTL, HCSL.

5, 14, 19

GND

Power

Power supply ground.

PLL_SEL

Input

Pullup

PLL select. Determines if the PLL is in bypass or enabled mode (default). In

enabled mode, the output frequency = VCO frequency/QDIV divider. In

bypass mode, the output frequency = reference clock frequency/(PDIV

*QDIV). LVCMOS/LVTTL interface levels.

8, 26

Unused

No internal connection.

FBO_DIV

Input

Pulldown

Output Divider Control for the feedback output pair, FBOUT, nFBOUT.

Determines if the output divider = ÷4 (default), or ÷5. Refer to Table 3D.

LVCMOS/LVTTL interface levels.

Input

Pulldown

Active High master reset. When logic HIGH, the internal dividers are reset

causing all the true outputs Qx to drive High-impedance. Note that assertion

of MR overrides the OE[2:0] control pins and all outputs are disabled. When

logic LOW, the internal dividers are enabled and the state of the outputs are

determined by OE[2:0]. MR must be asserted on power-up to ensure

outputs phase aligned. LVCMOS/LVTTL interface levels.

OE0

Input

Pullup

Output Enable. Together with OE1 and OE2, determines the output state of

the outputs with the default state: all output pairs switching. It should also be

noted that the feedback output pins (FBOUT, nFBOUT) are always

switching and are not affected by the state of OE[2:0]. Refer to Table 3B for

truth table. LVCMOS/LVTTL Interface levels.

OE1

Input

Pullup

Output Enable. Together with OE0 and OE2, determines the output state of

the outputs with the default state: all output pairs switching. It should also be

noted that the feedback output pins (FBOUT, nFBOUT) are always

switching and are not affected by the state of OE[2:0]. Refer to Table 3B for

truth table. LVCMOS/LVTTL Interface levels.

OE2

Input

Pullup

Output Enable. Together with OE0 and OE1, determines the output state of

the outputs with the default state: all output pairs switching. It should also be

noted that the feedback output pins (FBOUT, nFBOUT) are always

switching and are not affected by the state of OE[2:0]. Refer to table 3B for

truth table. LVCMOS/LVTTL Interface levels.

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