4

ICS951703

Byte 0: Control Register

(1 = enable, 0 = disable)

Byte 1: Control Register

(1 = enable, 0 = disable)

Byte 2: Control Register

(1 = enable, 0 = disable)

Notes:

1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be

configured at power-on and are not expected to be configured during the normal modes of operation.

2. PWD = Power on Default

3. Undefined bit can be wirtten with either a "1" or "0".

t

i

B#

n

i

Pe

m

a

ND

W

Pn

o

i

t

p

i

r

c

s

e

D

7

t

i

B6

3K

L

C

_

H

C

V1

*

)

e

v

i

t

c

a

n

I

/

e

v

i

t

c

A

(

6

t

i

B9

42

U

P

C1

)

e

v

i

t

c

a

n

I

/

e

v

i

t

c

A

(

5

t

i

B0

51

U

P

C1

)

e

v

i

t

c

a

n

I

/

e

v

i

t

c

A

(

4

t

i

B2

50

U

P

C1

)

e

v

i

t

c

a

n

I

/

e

v

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t

c

A

(

3

t

i

B>

<

m

u

r

t

c

e

p

S

d

a

e

r

p

S

)

d

e

l

b

a

n

e

=

1

(

1)

e

v

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t

c

a

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I

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e

v

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c

A

(

2

t

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B6

22

_

z

H

M

8

41

)

e

v

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t

c

a

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I

/

e

v

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A

(

1

t

i

B5

21

_

z

H

M

8

41

)

e

v

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t

c

a

n

I

/

e

v

i

t

c

A

(

0

t

i

B-

d

e

v

r

e

s

e

R0

)

e

v

i

t

c

a

n

I

/

e

v

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t

c

A

(

t

i

B#

n

i

Pe

m

a

ND

W

Pn

o

i

t

p

i

r

c

s

e

D

7

t

i

B-

d

e

v

r

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s

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R0

)

e

v

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t

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a

n

I

/

e

v

i

t

c

A

(

6

t

i

B-

d

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v

r

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R0

)

e

v

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t

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a

n

I

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v

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A

(

5

t

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B9

35

M

A

R

D

S1

)

e

v

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t

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a

n

I

/

e

v

i

t

c

A

(

4

t

i

B0

44

M

A

R

D

S1

)

e

v

i

t

c

a

n

I

/

e

v

i

t

c

A

(

3

t

i

B2

43

M

A

R

D

S1

)

e

v

i

t

c

a

n

I

/

e

v

i

t

c

A

(

2

t

i

B3

42

M

A

R

D

S1

)

e

v

i

t

c

a

n

I

/

e

v

i

t

c

A

(

1

t

i

B5

41

M

A

R

D

S1

)

e

v

i

t

c

a

n

I

/

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v

i

t

c

A

(

0

t

i

B6

40

M

A

R

D

S1

)

e

v

i

t

c

a

n

I

/

e

v

i

t

c

A

(

Notes:

Reserved bits must be wirtten as "0".

*Readback of the bit is always "0".

t

i

B#

n

i

Pe

m

a

ND

W

Pn

o

i

t

p

i

r

c

s

e

D

7

t

i

B9

2

-

6

6

V

31

)

e

v

i

t

c

a

n

I

/

e

v

i

t

c

A

(

6

t

i

B8

1

-

6

6

V

31

)

e

v

i

t

c

a

n

I

/

e

v

i

t

c

A

(

5

t

i

B7

0

-

6

6

V

31

)

e

v

i

t

c

a

n

I

/

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v

i

t

c

A

(

4

t

i

B-

d

e

v

r

e

s

e

R0

)

e

v

i

t

c

a

n

I

/

e

v

i

t

c

A

(

3

t

i

B-

d

e

v

r

e

s

e

R0

)

e

v

i

t

c

a

n

I

/

e

v

i

t

c

A

(

2

t

i

B-

d

e

v

r

e

s

e

R0

)

e

v

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a

n

I

/

e

v

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A

(

1

t

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B-

d

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R0

)

e

v

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a

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I

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v

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A

(

0

t

i

B-

d

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v

r

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s

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R0

)

e

v

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t

c

a

n

I

/

e

v

i

t

c

A

(