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80KSW0005BRI Datasheet(PDF) 1 Page - Renesas Technology Corp |
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80KSW0005BRI Datasheet(HTML) 1 Page - Renesas Technology Corp |
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1 / 50 page  1 of 49 January 18, 2011 DSC 5697 2010 Integrated Device Technology, Inc. All rights reserved. 1 Device Overview The CPS-10Q (80KSW0005) is a serial RapidIO switch whose functionality is central to routing packets for distribution among DSPs, processors, FPGAs, other switches, or any other sRIO-based devices. The CPS-10Q supports serial RapidIO packet switching (unicast, multicast, and an optional broadcast) from any of its 16 input ports to any of its 16 output ports. 2 Features u Interfaces - sRIO – 40 bidirectional serial RapidIO (sRIO) lanes v 1.3 – Port Speeds selectable: 3.125Gbps, 2.5Gbps, or 1.25Gbps – All lanes support short haul or long haul reach for each PHY speed – Configurable port count to up to 16 ports – Two enhanced quads can be configured as 4 1x ports or 1 4x ports – Supports standard 4 levels of priority – Error handling support: It allows error detection, logging and response from all major functional blocks on the device. u Interfaces - I2C – Provides I2C port for maintenance and error reporting – Master or Slave Operation – Master allows power-on configuration from external ROM – Master mode configuration with external image compressing and checksum u Performance – 100 Gbps of peak switching bandwidth – Non-blocking data flow architecture within each sRIO priority – low latency for all packet length and load condition – Internal queuing buffer and retransmit buffer – Standard receiver based physical layer flow control u Features – Configurable for cut-thru and store-and-forward modes – Device configurable through any of sRIO ports, I2C, or JTAG – Packet Trace function: It allows copying or filtering packets on a per- port basis. Each port provides the ability to match the first 160 bits of any packet against up to 4 programmable comparison values to copy the packet to a programmable output trace port or drop it. – Supports up to 40 simultaneous multicast masks per each port – Support Broadcast – Port Loopback Debug Feature – Software assisted error recovery, supporting hot swap – Ports may be individually turned off to reduce power – PMON counters for monitor and diagnostics per port – Serdes physical diagnostic registers – Embedded PRBS generation and detection with programmable poly- nomial cover error rate under all conditions – 0.13um technology – Low power dissipation – Full JTAG Boundary Scan support (IEEE1149.1 & 1149.6) – Package: FCBGA 676-ball grid array, 27mm x 27mm, 1.0mm ball pitch 3 Block Diagram Figure 1 Block diagram Maintenance & Error Management Configuration JTAG I2C sRIO Q5 Standard (1 port) sRIO Q8 Standard (1 port) sRIO Q6 Standard (1 port) sRIO Q7 Standard (1 port) sRIO Q9 Enhanced (1 or 4 ports) sRIO Q0 Standard (1 port) sRIO Q1 Standard (1 port) sRIO Q2 Standard (1 port) sRIO Q3 Standard (1 port) sRIO Q4 Enhanced (1 or 4 ports) Ln38 Ln39 Ln36 Ln37 Ln34 Ln35 Ln32 Ln33 Ln26 Ln27 Ln24 Ln25 Ln1 Ln0 Ln3 Ln2 Ln30 Ln31 Ln28 Ln29 Ln5 Ln4 Ln7 Ln6 Ln9 Ln8 Ln11 Ln10 Ln13 Ln12 Ln15 Ln14 Ln17 Ln16 Ln19 Ln18 Ln21 Ln20 Ln23 Ln22 Serial RapidIO Switch CPS-10Q Datasheet 80KSW0005 10-Quad RapidIO® Switch |
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