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87421 Datasheet(PDF) 5 Page - Renesas Technology Corp

Part # 87421
Description  ÷1/÷2 Differential-to-LVDS Clock Generator
PDF  16 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

87421 Datasheet(HTML) 5 Page - Renesas Technology Corp

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87421 Data Sheet
©2016 Integrated Device Technology, Inc
June 24, 2016
5
ADDITIVE PHASE JITTER
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the dBc Phase
Noise. This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase
noise is defined as the ratio of the noise power present in a 1Hz
band at a specified offset from the fundamental frequency to the
power value of the fundamental. This ratio is expressed in decibels
As with most timing specifications, phase noise measurements have
issues.The primary issue relates to the limitations of the equipment.
Often the noise floor of the equipment is higher than the noise floor
(dBm) or a ratio of the power in the 1Hz band to the power in the
fundamental. When the required offset is specified, the phase noise
is called a dBc value, which simply means dBm at a specified offset
from the fundamental. By investigating jitter in the frequency domain,
we get a better understanding of its effects on the desired application
over the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
of the device. This is illustrated above. The device meets the noise
floor of what is shown, but can actually be lower. The phase noise
is dependant on the input source and measurement equipment.
OFFSET FROM CARRIER FREQUENCY (HZ)
Additive Phase Jitter @
155.52MHz (12kHz to 20MHz) = 0.17ps typical



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