87421 Data Sheet

©2016 Integrated Device Technology, Inc

June 24, 2016

2

TABLE 1. PIN DESCRIPTIONS

TABLE 2. PIN CHARACTERISTICS

TABLE 3. FUNCTION TABLE

FIGURE 1A. ÷1 CONFIGURATION TIMING DIAGRAM

Number

Name

Type

Description

1

CLK

Input

Pulldown Non-inverting differential clock input.

2

nCLK

Input

Pullup

Inverting differential clock input.

3

MR

Input

Pulldown

Active High Master Reset. When logic HIGH, the internal dividers are

reset causing the true output (Q) to go low and the inverted output (nQ)

to go high. When logic LOW, the internal dividers and the output are

enabled. LVCMOS / LVTTL interface levels. See Table 3.

4

F_SEL

Input

Pulldown

Selects divider value for Q, nQ outputs as described in Table 3.

LVCMOS / LVTTL interface levels.

5

GND

Power

Power supply ground.

6, 7

Q, nQ

Output

Differential output pair. LVDS interface levels.

8V

DD

Power

Positive supply pin.

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

C

IN

Input Capacitance

4

pF

R

PULLUP

Input Pullup Resistor

51

k

Ω

R

PULLDOWN

Input Pulldown Resistor

51

k

Ω

MR

F_SEL

Divide Value

1

X

Reset: Q output low, nQ output high

00

÷1

01

÷2

CLK

MR

Q

FIGURE 1B. ÷2 CONFIGURATION TIMING DIAGRAM