FXPS7115D4 datasheet(14/72 Pages) NXP

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NXP Semiconductors

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

7.4.4 I2C acknowledge and not acknowledge transmissions

Each byte must be followed by an acknowledge bit (ACK) from the receiver. For an ACK, the transmitter

releases SDA during the acknowledge clock pulse and the receiver pulls SDA low during the high portion of the

clock pulse. Set up and hold times as specified in Table 105 must also be taken into account.

For a not acknowledge bit (NACK), SDA remains high during the entire acknowledge clock pulse. Five

conditions lead to a NACK:

1. No receiver is present on the bus with the transmitted address.

2. The addressed receiver is unable to receive or transmit because it is performing some real-time function

and is not ready to start communication with the host.

3. The receiver receives unrecognized data or commands.

4. The receiver cannot receive any more data bytes.

5. The host-receiver signals the end of the transfer to the client transmitter.

Following a NACK, the host can transmit either a STOP to terminate the transfer, or a repeated START to

initiate a new transfer.

An example ACK and NACK are shown in Figure 17.

aaa-029749

SDA

SCL

ACK

ninth clock pulse

ACK

ninth clock pulse

Figure 17. I2C acknowledge and not acknowledge transmission

7.4.5 I2C stop condition

A bus operation is always terminated with a stop condition (STOP) from the host. A STOP is defined as a low

to high transition on SDA while SCL is high as shown in Figure 18. After the STOP has been transmitted by the

host, the bus is considered free. Timing for the stop condition is specified in Table 105.

aaa-029750

SDA

SCL

STOP

Figure 18. I2C stop condition

7.4.6 I2C register transfers

7.4.6.1 Register write transfers

The device supports I2C register write data transfers. Register write data transfers are constructed as follows:

1. The host transmits a START condition.

FXPS7115D4

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Product data sheet

Rev. 6.2 — 28 June 2023

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