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FXPS7115D4 Datasheet(PDF) 50 Page - NXP Semiconductors |
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FXPS7115D4 Datasheet(HTML) 50 Page - NXP Semiconductors |
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50 / 72 page ![]() NXP Semiconductors FXPS7115D4 Digital absolute pressure sensor, 40 kPa to 115 kPa Bit 7 6 5 4 3 2 1 0 Symbol SN[7:0] Reset N/A N/A N/A N/A N/A N/A N/A N/A Access R R R R R R R R Table 94. SN3 Register (address C9h) bit allocation Bit 7 6 5 4 3 2 1 0 Symbol SN[7:0] Reset N/A N/A N/A N/A N/A N/A N/A N/A Access R R R R R R R R Table 95. SN4 Register (address CAh) bit allocation 7.7.27 ASIC wafer ID registers The ASIC wafer ID registers are factory programmed OTP registers that include the wafer number, wafer X and Y coordinates and the wafer lot number for the device ASIC. These registers are included in the factory programmed OTP array error detection. These registers are readable in SPI mode or I2C mode when ENDINIT is not set. Bit 7 6 5 4 3 2 1 0 Symbol ASICWFR#[7:0] Reset N/A N/A N/A N/A N/A N/A N/A N/A Access R R R R R R R R Table 96. ASICWFR# Register (address CBh) bit allocation Bit 7 6 5 4 3 2 1 0 Symbol ASICWFR_X[7:0] Reset N/A N/A N/A N/A N/A N/A N/A N/A Access R R R R R R R R Table 97. ASICWFR_X Register (address CCh) bit allocation Bit 7 6 5 4 3 2 1 0 Symbol ASICWFR_Y[7:0] Reset N/A N/A N/A N/A N/A N/A N/A N/A Access R R R R R R R R Table 98. ASICWFR_Y Register (address CDh) bit allocation Bit 7 6 5 4 3 2 1 0 Symbol ASICWLOT_L[7:0] Reset N/A N/A N/A N/A N/A N/A N/A N/A Access R R R R R R R R Table 99. ASICWLOT_L Register (address D0h) bit allocation FXPS7115D4 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved. Product data sheet Rev. 6.2 — 28 June 2023 50 / 72 |
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