FXPS7115D4 datasheet(17/72 Pages) NXP

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NXP Semiconductors

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

7.5 Standard 32-bit SPI protocol

The device includes a standard SPI protocol requiring 32-bit data packets. The device is a client device

and requires a low base clock value (CPOL = 0) with data captured on the rising edge of the clock and data

propagated on the falling edge of the clock (CPHA = 0). The most significant bit is transferred first (MSB

first). SPI transfers are completed through a sequence of two phases. During the first phase, the command is

transmitted from the SPI host to the device. During the second phase, response data is transmitted from the

client device. MOSI and SCLK transitions are ignored when SS_B is not asserted.

SCLK

SS_B

MOSI

MISO

SCLK

SS_B

MISO

MOSI

phase two response

phase one: response-previous command

phase one: command

aaa-023747

Figure 20. Standard 32 Bit SPI protocol timing diagram

7.5.1 SPI command format

There are two SPI commands as shown in Table 10. These are the Register Access command and the Sensor

Data command.

The Register Access command is a standard SPI read and write command which access the registers and are

defined by field descriptions shown in Section 7.5.3.1 through Section 7.5.3.2.

The Sensor Data command provides additional information such as basic and detailed sensor status if needed

as defined by field descriptions shown in Section 7.5.3.3.

FXPS7115D4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6.2 — 28 June 2023

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FXPS7115D4 Datasheet(PDF) 17 Page - NXP Semiconductors