CS5305GDWR28 datasheet(24/33 Pages) ONSEMI

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CS5305

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Figure 40.

−

RFB

VDRP

V(DAC)

VOUT

OUTPUT

STAGE

RDRP

I(VFB)

VFB

As was previously noted, the total value of resistance

between the ROSC pin and ground sets the VFB lead bias

current according to:

I(VFB) + 0.333 V (ROSC ) ROCSET)

Referring to Figure 40, the VDRP lead voltage is equal to

the DAC voltage plus the current sense information. Under

no load conditions, the VDRP and VFB pin voltages are equal,

and the entire VFB bias current flows between

VOUT(SENSE)+ and VFB through RFB. Because the VFB bias

current sinks into VFB, the output voltage is forced to be

higher than the DAC voltage, and so the value of RFB can be

calculated as:

RFB + (VOUT no load set point * VDAC) I(VFB)

With RFB chosen, we can now select the value of RDRP.

If we again refer to Figure 40, we can use Kirchoff’s

Current Law at the VFB node to find that the value of RDRP

is defined as:

RDRP +

(full load current)(3.7)(ESRL)(RFB)

(RFB)(I(VFB)) ) V(DAC) * VOUT full load set point

RVSENSE is used to ensure that a connection between

VOUT and VOUT(SENSE) always exists. This ensures that the

module will operate correctly in the event that the

VOUT(SENSE) connection is broken. The module−to−load

interface and the number of modules placed in parallel

determine the value of RVSENSE. The CS5305 is specified to

operate correctly with up to 55 mV dropped across the

module connector. It is assumed that the maximum current

allowed to flow in this connection to the load is 1 mA.

RVSENSE + 55 mV (1 mA N)

where:

N = the number of modules to be paralleled.

If four modules are to be paralleled, each contributes a

maximum of 250 μA to this connection, and so RVSENSE =

55 mV/250 μA = 220 Ω. This component is placed to ensure

the VRM module will regulate correctly if the module

VOUT(SENSE)+ connection to the load is opened.

The transient droop performance should be checked next.

Performance should be verified using the transient test tool

typically provided in a microprocessor development kit.

True transient performance can be masked even at test

frequencies as low as 2 kHz. It should be possible to modify

the test tool so a function generator can drive it. Using lower

frequency (approximately 100 Hz) and lower duty cycle

(10%) allow the designer to better observe the true settling

behavior of the VRM module.

It may be necessary to add some filtering components to

the droop voltage divider. These components cause the AC

and DC gain from the current sense circuitry to match and

allow the user to tailor the droop output voltage

performance.

There are two methods for tuning droop performance. The

first is illustrated in Figure 41. In this case, capacitors CDRP

and CFB are placed in parallel with RDRP and RFB. A third

capacitor CDRCMP is connected between the COMP and

VDRP leads. The first two capacitors correct any gain errors

introduced in the selection of current sense components

Rcsx and Ccsx. Values for these components are defined as:

CFB + L ((RFB)(ESRL))

and

CDRP + ((CCSx)(RCSx)) RDRP

The capacitor between VDRP and COMP allows the user

to fine−tune the transition between “fast” AVP and the

slower positioning set by resistors RDRP and RFB. This

capacitor may or may not be required and is empirically

chosen based on the fine−tuning procedure described below.

A value of 1 nF is recommended as an initial value.

Figure 41.

RDRP

RFB

RVSENSE

VOUT

VOUT(SENSE)+

VFB

VDRP

CDRP

CFB

CDRCMP

COMP

Set up the circuit to be tested with a DVM and

oscilloscope to the output. Have the scope set to DC input

and set its offset so a resolution of at least 100 mV/div is used

and the output is visible on the screen.

Using a DVM, measure the output voltage with no load.

If this value differs from the expected value, adjust RFB until

the nominal value is reached. Once this is set, mark this DC

level on the scope with a cursor.

Next, measure the output voltage with full DC load. If this

value deviates from the expected value, adjust RDRP until

the nominal value is reached. Once this is set, mark this DC

level on the scope with another cursor.

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