AD5362BSTZ datasheet(19/25 Pages) AD

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Preliminary Technical Data

AD5362/AD5363

Rev. P

rF | Page 19 of 25

Table 7. AD5362 Serial Word Bit Assignation

I23

I22

I21

I20

I19

I18

I17

I16

I15

I14

I13

I12

I11

I10

D15

D14

D13

D12

D11

D10

Table 8. AD5363 Serial Word Bit Assignation

I23

I22

I21

I20

I19

I18

I17

I16

I15

I14

I13

I12

I11

I10

I1*

I0*

D13

D12

D11

D10

M1 and M0 are mode bits.

A5 is an unused address bit and must always be written as 0.

A4 to A0 are address bits.

D15 to D0 are data bits.

*In the AD5363, bits I1 and I0 are only used in Special Function Mode

SPI READBACK MODE

The AD5362/AD5363 allows data readback via the serial

interface from every register directly accessible to the serial

interface, which is all registers except the X2A, X2B and DAC

registers. In order to read back a register, it is first necessary to

tell the AD5362/AD5363 which register is to be read. This is

achieved by writing to the device a word whose first two bits are

the special function code 00. The remaining bits then

determine if the operation is a readback, and the register which

is to be read back, or if it is a write to of the special function

registers such as the control register.

After the special function write has been performed, if it is a

readback command then data from the selected register will be

clocked out of the SDO pin during the next SPI operation. The

SDO pin is normally three-state but becomes driven as soon as

a read command has been issued. The pin will remain driven

until the registers data has been clocked out. See Figure 5 for

the read timing diagram. Note that due to the timing

requirements of t5 (25ns) the maximum speed of the SPI

interface during a read operation should not exceed 20MHz.

CHANNEL ADDRESSING AND SPECIAL MODES

If the mode bits are not 00, then the data word D15 to D0 is

written to the device. Address bits A4 to A0 determine which

channel or channels is/are written to, while the mode bits

determine to which register (X1A, X1B, C or M) the data is

written, as shown in Table 7. If data is to be written to the X1A

or X1B register, the setting of the A/B bit in the Control

X1A, 1

X1B).

Table 9. Mode Bits

Action

Write DAC input data (X1A or X1B) register,

depending on Control Register A/B bit.

Write DAC offset (C) register

Write DAC gain (M) register

Special function, used in combination with other

bits of word

The AD5362/AD5363 has very flexible addressing that allows

writing of data to a single channel, all channels in a group, the

same channel in groups 0 and 1, or all channels in the device.

Table 11 shows all these address modes.

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