Preliminary Technical Data

AD5371

Rev. P

rF | Page 11 of 25

Table 5. Pin Function Descriptions

Pin

Function

Logic Power Supply; 2.5 V to 5.5 V. These pins should be decoupled with 0.1 µF ceramic capacitors and 10 µF

capacitors.

Negative Analog Power Supply; −4.5 V to −16.5 V for specified performance. These pins should be decoupled with 0.1

µF ceramic capacitors and 10 µF capacitors.

Positive Analog Power Supply; +8 V to +16.5 V for specified performance. These pins should be decoupled with 0.1 µF

ceramic capacitors and 10 µF capacitors.

AGND

Ground for All Analog Circuitry. All AGND pins should be connected to the AGND plane.

DGND

Ground for All Digital Circuitry. All DGND pins should be connected to the DGND plane.

Reference Input for DACs 0 to 7. This reference voltage is referred to AGND.

Reference Input for DACs 8 to 15. reference This voltage is referred to AGND.

Reference Input for DACs 16 to 39. This reference voltage is referred to AGND.

VOUT0 to VOUT39

DAC Outputs. Buffered analog outputs for each of the 40 DAC channels. Each analog output is capable of driving an

output load of 10 kΩ to ground. Typical output impedance of these amplifiers is 0.5 Ω.

SYNC

Active Low or Differential SYNC Input (Complement) for SPI or LVDS Interface. This is the frame synchronization signal

for the SPI or LVDS serial interface. See SPI and LVDS timing diagrams and descriptions for more details.

SCLK

Serial Clock Input for SPI or LVDS Interface. See SPI and LVDS timing diagrams and descriptions for more details.

SDI

Serial Data Input for SPI or LVDS Interface. See SPI and LVDS timing diagrams and descriptions for more details.

SDO

Serial Data Output for SPI Interface. CMOS output. SDO can be used for readback. Data is clocked out on SDO on the

rising edge of SCLK and is valid on the falling edge of SCLK.

SYNC

Differential SYNC Input for LVDS Interface . This is the frame synchronization signal for the LVDS serial interface. See

LVDS timing diagram and description for more details.

SCLK

Differential Serial Clock Input (Complement) for LVDS Interface. See LVDS timing diagrams and descriptions for more

details.

SDI

Differential Serial Data Input (Complement) for LVDS Interface. See LVDS timing diagrams and descriptions for more

details.

CLR

Asynchronous Clear Input (level sensitive, active low). See the Clear Function section for more information

SPI/LVDS

Selects between SPI (low) or LVDS (high) serial interface.

LDAC

Load DAC Logic Input (active low). See the BUSY AND LDAC FUNCTIONS section for more information

BUSY

Digital Input/Open-Drain Output. BUSY is open-drain when an output. See the BUSY AND LDAC FUNCTIONS section

for more information

RESET

Asynchronous Digital Reset Input.

SIGGND0

Reference Ground for DACs 0 to 7. VOUT0 to VOUT7 are referenced to this voltage.

SIGGND1

Reference Ground for DACs 8 to 15. VOUT8 to VOUT15 are referenced to this voltage.

SIGGND1

Reference Ground for DACs 16 to 23. VOUT16 to VOUT23 are referenced to this voltage.

SIGGND3

Reference Ground for DACs 24 and 31. VOUT24 to VOUT31 are referenced to this voltage.

SIGGND4

Reference Ground for DACs 32 to 39. VOUT32 to VOUT39 are referenced to this voltage.

TESTI

Test Input Pin. This pin should be connected to DGND

TESTO

Test Output Pin. This pin should be left unconnected