AD5371BBCZ datasheet(17/25 Pages) AD

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Preliminary Technical Data

AD5371

Rev. P

rF | Page 17 of 25

goes high. BUSY also goes low, for approximately 500ns,

whenever the A/B Select Registers are written to.

The BUSY pin is bidirectional and has a 50 kΩ internal pullup

resistor. Where multiple AD5371 devices may be used in one

system the BUSY pins can be tied together. This is useful where

it is required that no DAC in any device is updated until all

other DACs are ready. When each device has finished updating

the X2 (A or B) registers it will release the BUSY pin. If another

device hasn’t finished updating its X2 registers it will hold BUSY

low, thus delaying the effect of LDAC going low.

The DAC outputs are updated by taking the LDAC input low. If

LDAC goes low while BUSY is active, the LDAC event is stored

and the DAC outputs update immediately after BUSY goes

high. A user can also hold the LDAC input permanently low. In

this case, the DAC outputs update immediately after BUSY

goes high.

As described later, the AD5371 has flexible addressing that

allows writing of data to a single channel, all channels in a

group, the same channel in groups 0 to 4 or groups 1 to 4, or all

channels in the device. This means that 1, 5, 8 or 40 X2 register

values may need to be calculated and updated. As there is only

one multiplier shared between 40 channels, this task must be

done sequentially, so the length of the BUSY pulse will vary

according to the number of channels being updated.

Table 7. BUSY Pulse Widths

Action

BUSY Pulse

Width (µs max)

Loading X1A, X1B, C, or M to 1 channel

1.25

Loading X1A, X1B, C, or M to 5 channels

3.25

Loading X1A, X1B, C, or M to 8 channels

4.75

Loading X1A, X1B, C, or M to 40 channels

20.75

BUSY Pulse Width = ((Number of Channels +1) × 500ns) +250ns

The AD5371 contains an extra feature whereby a DAC register

is not updated unless its X2A or X2B register has been written

to since the last time LDAC was brought low. Normally, when

LDAC is brought low, the DAC registers are filled with the

contents of the X2A or X2B registers, depending on the setting

of the A/B Select Registers. However the AD5371 updates the

DAC register only if the X2 data has changed, thereby

removing unnecessary digital crosstalk.

POWER-DOWN MODE

The AD5371 can be powered down by setting Bit 0 in the

control register. This will turn off the DACs thus reducing the

current consumption. The DAC outputs will be connected to

their respective SIGGND potentials. The power-down mode

doesn’t change the contents of the registers and the DACs will

return to their previous voltage when the power-down bit is

cleared.

THERMAL MONITOR FUNCTION

The AD5371 can be programmed to power down the DACs if

the temperature on the die exceeds 130°C. Setting Bit 1 in the

control register (see Table 12) will enable this function. If the

die temperature exceeds 130°C the AD5371 will enter a

temperature power-down mode, which is equivalent to setting

the power-down bit in the control register. To indicate that the

AD5371 has entered temperature shutdown mode Bit 4 of the

control register is set. The AD5371 will remain in temperature

shutdown mode, even if the die temperature falls, until Bit 1 in

the control register is cleared.

TOGGLE MODE

The AD5371 has two X2 registers per channel, X2A and X2B,

which can be used to switch the DAC output between two levels

with ease. This approach greatly reduces the overhead required

by a micro-processor which would otherwise have to write to

each channel individually. When the user writes to either the

X1A ,X2A, M or C registers the calculation engine will take a

certain amount of time to calculate the appropriate X2A or X2B

values. If the application only requires that the DAC output

switch between two levels, such as a data generator, any method

which reduces the amount of calculation time encountered is

advantageous. For the data generator example the user need

only set the high and low levels for each channel once, by

writing to the X1A and X1B registers. The values of X2A and

X2B will be calculated and stored in their respective registers.

The calculation delay therefore only happens during the setup

phase, i.e. when programming the initial values. To toggle a

DAC output between the two levels it is only required to write

to the relevant A/B Select Register to set the MUX2 register bit.

Furthermore, since there are 8 MUX2 control bits per register it

is possible to update eight channels with a single write. Table 14

shows the bits that correspond to each DAC output.

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