AD7631/AD7634

Preliminary Technical Data

Rev. PrC | Page 10 of 14

Pin

No.

Mnemonic

Type1

Description

11, 12

D[4:5]

DI/O

When MODE[1:0] = 0, 1, or 2, these pins are Bit 4 and Bit 5 of the parallel port data output bus.

or DIVSCLK[0:1]

When MODE[1:0] = 3 (serial mode), serial clock division selection. When using serial master read

after convert mode (EXT/INT = low, RDC/SDIN = low), these inputs can be used to slow down the

internally generated serial clock that clocks the data output. In other serial modes, these pins are

high impedance outputs.

13

D6

DI/O

When MODE[1:0] = 0, 1, or 2, this output is used as Bit 6 of the parallel port data output bus.

or EXT/INT

When MODE[1:0] = 3 (serial mode), serial clock source select. This input is used to select the

internally generated (master) or external (slave) serial data clock.

When EXT/INT = low, master mode. The internal serial clock is selected on SCLK output.

When EXT/INT = high, slave mode. The output data is synchronized to an external clock signal,

gated by CS, connected to the SCLK input.

14

D7

DI/O

When MODE[1:0] = 0, 1, or 2, this output is used as Bit 7 of the parallel port data output bus.

or INVSYNC

When MODE[1:0] = 3 (serial mode), invert sync select. In serial master mode (EXT/INT = low), this

input is used to select the active state of the SYNC signal.

When INVSYNC = low, SYNC is active high.

When INVSYNC = high, SYNC is active low.

15

D8

DI/O

When MODE[1:0] = 0, 1, or 2, this output is used as Bit 8 of the parallel port data output bus.

or INVSCLK

When MODE[1:0] = 3, invert SCLK select. In all serial modes, this input is used to

invert the SCLK signal.

16

D9

DI/O

When MODE[1:0] = 0, 1, or 2, this output is used as bit 9 of the parallel port data output bus.

or RDC

When MODE[1:0] = 3 (serial mode), read during convert. When using serial master mode

(EXT/INT = low), RDC is used to select the read mode.

When RDC = high, the previous conversion result is output on SDOUT during conversion and

the period of SCLK changes.

When RDC = low (read after convert), the current result can be output on SDOUT only when

the conversion is complete.

or SDIN

When MODE[1:0] = 3 (serial mode), serial data in. When using serial slave mode, (EXT/INT = high),

SDIN could be used as a data input to daisy-chain the conversion results from two or more ADCs

onto a single SDOUT line. The digital data level on SDIN is output on SDOUT with a delay of 18 SCLK

periods after the initiation of the read sequence.

17

OGND

P

Input/Output Interface Digital Power Ground.

18

OVDD

P

Input/Output Interface Digital Power. Nominally at the same supply as the supply of the

host interface (2.7 V to 5V).

19

DVDD

P

Digital Power. Nominally at 5 V.

20

DGND

P

Digital Power Ground.

21

D10

DO

When MODE[1:0] = 0, 1, or 2, this output is used as Bit 10 of the parallel port data output bus.

or SDOUT

When MODE[1:0] = 3 (serial mode), serial data output. In serial mode, this pin is used as the serial

data output synchronized to SCLK. Conversion results are stored in an on-chip register. The ADC

provides the conversion result, MSB first, from its internal shift register. The data format is

determined by the logic level of OB/2C.

In master mode, EXT/INT = low. SDOUT is valid on both edges of SCLK.

In slave mode, EXT/INT = high:

When INVSCLK = low, SDOUT is updated on SCLK rising edge and valid on the next falling edge.

When INVSCLK = high, SDOUT is updated on SCLK falling edge and valid on the next rising edge.

22

D11

DI/O

When MODE[1:0] = 0, 1, or 2, this output is used as Bit 11 of the parallel port data output bus.

or SCLK

When MODE[1:0] = 3 (serial mode), serial clock. In all serial modes, this pin is used as the serial

data clock input or output, depending upon the logic state of the EXT/INT pin. The active edge

where the data SDOUT is updated depends on the logic state of the INVSCLK pin.

23

D12

DO

When MODE[1:0] = 0, 1, or 2, this output is used as Bit 12 of the parallel port data output bus.

or SYNC

When MODE[1:0] = 3 (serial mode), frame synchronization. In serial master mode (EXT/INT= low),

this output is used as a digital output frame synchronization for use with the internal data clock.