Preliminary Technical Data

AD7631/AD7634

Rev. PrC | Page 11 of 14

Pin

No.

Mnemonic

Type1

Description

When a read sequence is initiated and INVSYNC = low, SYNC is driven high and remains high

while SDOUT output is valid.

When a read sequence is initiated and INVSYNC = high, SYNC is driven low and remains low

while SDOUT output is valid.

24

D13

DO

When MODE[1:0] = 0, 1, or 2, this output is used as Bit 13 of the parallel port data output bus.

or RDERROR

When MODE[1:0] = 3 (serial mode), read error. In serial slave mode (EXT/INT = high), this output

is used as an incomplete read error flag. If a data read is started and not completed when the

current conversion is complete, the current data is lost and RDERROR is pulsed high.

25

D14

DI/O

When MODE[1:0] = 0, 1, or 2, this output is used as Bit 14 of the parallel port data output bus.

or HW/SW

When MODE[1:0] = 3 (serial mode) hardware/software select. This input, part of the serial

programmable port, is used to select hardware or software input ranges and mode selection.

26

D15

DI/O

When MODE[1:0] = 0, 1, or 2, this output is used as Bit 15 of the parallel port data output bus.

or SPPDATA

When MODE[1:0] = 3 (serial mode), serial programmable port data. This input is used to write in the

serial programmable port data when HW/SW = low.

27

D16

DI/O

When MODE[1:0] = 0, 1, or 2, this output is used as Bit 16 of the parallel port data output bus.

or SPPCLK

When MODE[1:0] = 3 (serial mode), serial programmable port clock. This input is used to clock in the

data on SPPDATA. The active edge where the data SPPDATA is updated depends on the logic state of

the INVSCLK pin.

28

D17

DI/O

When MODE[1:0] = 0, 1, or 2, this output is used as Bit 17 of the parallel port data output bus.

or SPPEN

When MODE[1:0] = 3 (serial mode), serial programmable port enable. Asserting this input enables the

serial programmable port.

29

BUSY

DO

Busy Output. Transitions high when a conversion is started and remains high until the conversion

is complete and the data is latched into the on-chip shift register. The falling edge of BUSY can be

used as a data-ready clock signal.

30

TEN

DI

10 Volt Input Range. Refer to Table 8.

When MODE[1:0] = 0, 1, or 2, this input is used to select the 10V input range.

When MODE[1:0] = 3 (serial mode), and

HW/SW = high, driving TEN high selects the 10 Volt input range.

HW/SW = low, the input range is programmed with the serial programmable port and this pin is a

don’t care.

31

RD

DI

Read Data. When CS and RD are both low, the interface parallel or serial output bus is enabled.

32

CS

DI

Chip Select. When CS and RD are both low, the interface parallel or serial output bus is enabled.

CS is also used to gate the external clock in slave serial mode.

33

RESET

DI

Reset Input. When high, resets the ADC. Current conversion, if any, is aborted. Falling edge of

RESET enables the calibration mode indicated by pulsing BUSY high. If not used, this pin can be tied to

DGND.

34

PD

DI

Power-Down Input. When high, power downs the ADC. Power consumption is reduced and

conversions are inhibited after the current one is completed.

35

CNVST

DI

Conversion Start. A falling edge on CNVST puts the internal sample-and-hold into the hold state

and initiates a conversion.

36

BIP

DI

Bipolar Input Range. Refer to Table 8.

When MODE[1:0] = 0, 1, or 2, this input is used to select the bipolar input range.

When MODE[1:0] = 3 (serial mode), and

HW/SW = high, driving BIP high selects the bipolar input range.

HW/SW = low, the input range is programmed with the serial programmable port and this pin is a

don’t care.

37

REF

AI/O

Reference Output/Input.

When PDREF/PDBUF = low, the internal reference and buffer are enabled producing 5 V on this pin.

When PDREF/PDBUF = high, the internal reference and buffer are disabled allowing an externally

supplied voltage reference up to AVDD volts. Decoupling is required with or without the internal

reference and buffer.