ADPD7000 datasheet(92/127 Pages) AD

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Data Sheet

ADPD7000

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Rev. 0 | 92 of 127

Table 24. Register Details (Continued)

Reg

Name

Bits Bit Name

Description

Reset

Access

ECG_PGA_SAT_STATUS

ECG PGA saturation status bit. Write 1 to this bit

to clear this status.

0x0

R/W1C

ECG_ADC_SAT_STATUS

ECG ADC saturation status bit. Write 1 to this bit

to clear this status.

0x0

R/W1C

0x005

GLOBAL_STATUS

[15:

12]

RESERVED

Reserved.

0x0

ECG_RLD_LEADON_HI_STATUS

ECG RLD lead-on high status bit. Write 1 to this

bit to clear this status.

0x0

R/W1C

ECG_RLD_LEADON_LO_STATUS

ECG RLD lead-on low status bit. Write 1 to this bit

to clear this status.

0x0

R/W1C

ECGIN_LEADON_HI_STATUS

ECGIN lead-on high status bit. Write 1 to this bit to

clear this status.

0x0

R/W1C

ECGIP_LEADON_HI_STATUS

ECGIP lead-on high status bit. Write 1 to this bit to

clear this status.

0x0

R/W1C

[7:1] RESERVED

Reserved.

0x0

INVALID_CFG_STATUS

Status bit indicating that TIMESLOT_PERIOD_x is

not correctly configured. Write 1 to this bit to clear

this status.

0x0

R/W1C

0x006

FIFO_TH

[15:

10]

RESERVED

Reserved.

0x0

[9:0] FIFO_TH

FIFO interrupt generation threshold. Generate the

FIFO interrupt during a FIFO write when the

number of bytes in the FIFO exceeds this value.

0xC

R/W

0x007

INT_ACLEAR

INT_ACLEAR_FIFO

FIFO threshold Interrupt auto clear enabled. Set

this bit to enable automatic clearing of the

FIFO_TH interrupt each time the FIFO is read.

0x1

R/W

[14:

RESERVED

Reserved.

0x0

0x008

CHIP_ID

[15:

VERSION

Mask version. R0 = 0x0.

0x0

[7:0] CHIP_ID

Chip ID.

0xC6

0x009

OSC32M

[15:

RESERVED

Reserved.

0x0

OSC_32M_EFUSE_CTRL

Enables the high frequency oscillator frequency

control from the eFuse bits. Write 0 to this

bit to enable the frequency control from the

OSC_32M_FREQ_ADJ bits.

0x0

R/W

[7:0] OSC_32M_FREQ_ADJ

High frequency oscillator frequency control. 0x000

is the lowest frequency, 0x0FF is the maximum

frequency.

0x80

R/W

0x00A

OSC32M_CAL

OSC_32M_CAL_START

Start high frequency oscillator calibration cycle.

Writing a 1 to this bit causes the high frequency

oscillator calibration cycle to occur. It enables

the oscillator, waits for it to start, and then

counts the number 32 MHz cycles during either

128 (1 MHz) or 4 (32 kHz) low frequency

cycles based on which one is selected. It

updates the OSC_32M_CAL_COUNT bits with

this count. The calibration circuit clears the

OSC_32M_CAL_START bit when the calibration

cycle completes. Silicon Version 0 counts 32 low

frequency cycles if using the 32 kHz low frequency

oscillator.

0x0

R/W

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