GWIXP425BCT datasheet(45/134 Pages) INTEL

45 / 134 page

Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor

Datasheet

March 2005

Document Number: 252479, Revision: 005

Table 13.

UART Interfaces

Name

Power

Reset1

Reset2

Type†

Description

RXDATA0

UART serial data input to High-Speed UART Pins.

Should be pulled low through a 10-K

Ω resistor when not being

utilized in the system.

TXDATA0

UART serial data output. The TXD signal is set to the MARKING

(logic 1) state upon a reset operation. High-Speed Serial UART Pins.

CTS0_N

VI/PE

UART CLEAR-TO-SEND input to High-Speed UART Pins.

When logic 0, this pin indicates that the modem or data set

connected to the UART interface of the processor is ready to

exchange data. The CTS_N signal is a modem status input whose

condition can be tested by the processor.

Should be pulled high through a 10-K

Ω resistor when not being

utilized in the system.

RTS0_N

VO/PE

UART REQUEST-TO-SEND output:

When logic 0, this informs the modem or the data set connected to

the UART interface of the processor that the UART is ready to

exchange data. A reset sets the request to send signal to logic 1.

LOOP-mode operation holds this signal in its inactive state (logic 1).

High-Speed UART Pins.

RXDATA1

UART serial data input.

Should be pulled low through a 10-K

Ω resistor when not being

utilized in the system.

TXDATA1

UART serial data output. The TXD signal is set to the MARKING

(logic 1) state upon a Reset operation. Console UART Pins.

CTS1_N

VI/PE

UART CLEAR-TO-SEND input to Console UART pins.

When logic 0, this pin indicates that the modem or data set

connected to the UART interface of the processor is ready to

exchange data. The CTS_N signal is a modem status input whose

condition can be tested by the processor.

Should be pulled high through a 10-K

Ω resistor when not being

utilized in the system.

RTS1_N

VO/PE

UART REQUEST-TO-SEND output:

When logic 0, this informs the modem or the data set connected to

the UART interface of the processor that the UART is ready to

exchange data. A reset sets the request to send signal to logic 1.

LOOP-mode operation holds this signal in its inactive state (logic 1).

Console UART Pins.

While PWRON_RESET_N is deasserted use Power On Reset column for the pin state.

After deassertion of PWRON_RESET_N, and deassertion of RESET_IN_N, and assertion of

PLL_LOCK, all signals reflect the value shown in the RESET column.

†

For a legend of the Type codes, see Table 5 on page 33.

GWIXP425BCT Datasheet(PDF) 45 Page - Intel Corporation

GWIXP425BCT Datasheet(HTML) 45 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL