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MPC8560CPXAPDB Datasheet(PDF) 21 Page - Freescale Semiconductor, Inc

Part # MPC8560CPXAPDB
Description  Integrated Processor Hardware Specifications
PDF  108 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8560CPXAPDB Datasheet(HTML) 21 Page - Freescale Semiconductor, Inc

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MPC8560 Integrated Processor Hardware Specifications, Rev. 3.1
Freescale Semiconductor
21
DDR SDRAM
6.2 DDR SDRAM AC Electrical Characteristics
This section provides the AC electrical characteristics for the DDR SDRAM interface.
6.2.1 DDR SDRAM Input AC Timing Specifications
Table 14 provides the input AC timing specifications for the DDR SDRAM interface.
Figure 4. DDR SDRAM Interface Input Timing
6.2.2 DDR SDRAM Output AC Timing Specifications
6.2.2.1 DLL Enabled Mode
Table 15 and Table 16 provide the output AC timing specifications and measurement conditions for the DDR
SDRAM interface with the DDR DLL enabled.
Table 14. DDR SDRAM Input AC Timing Specifications
At recommended operating conditions with GVDD of 2.5 V ± 5%.
Parameter
Symbol
Min
Max
Unit
Notes
AC input low voltage
VIL
MVREF – 0.31
V
AC input high voltage
VIH
MVREF + 0.31
GVDD + 0.3
V
MDQS—MDQ/MECC input skew per byte
For DDR = 333 MHz
For DDR
≤ 266 MHz
tDISKEW
-750
-1125
750
1125
ps
1, 2
Note:
1.Maximum possible skew between a data strobe (MDQS[n]) and any corresponding bit of data (MDQ[8n + {0...7}] if 0
≤ n ≤ 7) or ECC (MECC[{0...7}] if n = 8).
2.For timing budget analysis, the MPC8560 consumes
±550 ps of the total budget.
Table 15. DDR SDRAM Output AC Timing Specifications - DLL Mode
At recommended operating conditions with GVDD of 2.5 V ± 5%.
Parameter
Symbol 1
Min
Max
Unit
Notes
MCK[n] cycle time, (MCK[n]/MCK[n] crossing)
tMCK
6
10
ns
2
On chip Clock Skew
tMCKSKEW
150
ps
3, 8
MDQS[n]
MDQ[n]
tDISKEW
tDISKEW



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