MPC8560CPXAPDB datasheet(85/108 Pages) FREESCALE

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MPC8560 Integrated Processor Hardware Specifications, Rev. 3.1

Freescale Semiconductor

Clocking

15.3 e500 Core PLL Ratio

Table 57 describes the clock ratio between the e500 core complex bus (CCB) and the e500 core clock. This ratio is

determined by the binary value of LALE and LGPL2 at power up, as shown in Table 57.

Table 56. CCB Clock Ratio

Binary Value of

LA[28:31]

Signals

Ratio Description

0000

16:1 ratio CCB clock: SYSCLK (PCI bus)

0001

Reserved

0010

2:1 ratio CCB clock: SYSCLK (PCI bus)

0011

3:1 ratio CCB clock: SYSCLK (PCI bus)

0100

4:1 ratio CCB clock: SYSCLK (PCI bus)

0101

5:1 ratio CCB clock: SYSCLK (PCI bus)

0110

6:1 ratio CCB clock: SYSCLK (PCI bus)

0111

Reserved

1000

8:1 ratio CCB clock: SYSCLK (PCI bus)

1001

9:1 ratio CCB clock: SYSCLK (PCI bus)

1010

10:1 ratio CCB clock: SYSCLK (PCI bus)

1011

Reserved

1100

12:1 ratio CCB clock: SYSCLK (PCI bus)

1101

Reserved

1110

Reserved

1111

Reserved

Table 57. e500 Core to CCB Ratio

Binary Value of

LALE, LGPL2

Signals

Ratio Description

2:1 e500 core:CCB

5:2 e500 core:CCB

3:1 e500 core:CCB

7:2 e500 core:CCB

MPC8560CPXAPDB Datasheet(PDF) 85 Page - Freescale Semiconductor, Inc

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