M58BW16F datasheet(24/81 Pages) STMICROELECTRONICS

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Bus operations

M58BW16F, M58BW32F

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Bus operations

Each bus operations that controls the memory is described in this section, see Tables 6 and

7 Bus Operations, for a summary. The bus operation is selected through the Burst

Configuration Register; the bits in this register are described at the end of this section.

On Power-up or after a Hardware Reset the memory defaults to Asynchronous Bus Read

and Asynchronous Bus Write. No synchronous operation can be performed until the Burst

Control Register has been configured.

The Electronic Signature, Block Protection Configuration, CFI or Status Register will be read

in asynchronous mode regardless of the Burst Control Register settings.

Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the

memory and do not affect bus operations.

3.1

Asynchronous Bus Operations

For asynchronous bus operations refer to Table 6 together with the following text. The read

access will start at whichever of the three following events occurs last: valid address

transition, Chip Enable, E, going Low, VIL or Latch Enable, L, going Low, VIL.

3.1.1

Asynchronous Bus Read

Asynchronous Bus Read operations read from the memory cells, or specific registers

(Electronic Signature, Block Protection Configuration Register, Status Register, CFI and

Burst Configuration Register) in the Command Interface. A valid bus operation involves

setting the desired address on the Address Inputs, applying a Low signal, VIL, to Chip

Enable and Output Enable and keeping Write Enable and Output Disable High, VIH. The

Data Inputs/Outputs will output the value, see Figure 7: Asynchronous Bus Read AC

waveforms, and Table 18: Asynchronous Bus Read AC characteristics, for details of when

the output becomes valid.

Asynchronous Read is the default read mode which the device enters on power-up or on

return from Reset/Power-Down.

3.1.2

Asynchronous Latch Controlled Bus Read

Asynchronous Latch Controlled Bus Read operations read from the memory cells or specific

registers in the Command Interface. The address is latched in the memory before the value

is output on the data bus, allowing the address to change during the cycle without affecting

the address that the memory uses.

A valid bus operation involves setting the desired address on the Address Inputs, setting

Chip Enable and Latch Enable Low, VIL and keeping Write Enable High, VIH; the address is

latched on the rising edge of Latch Enable. Once latched, the Address Inputs can change.

Set Output Enable Low, VIL, to read the data on the Data Inputs/Outputs; see Figure

Figure 8: Asynchronous Latch controlled bus Read AC waveforms and Table 18:

Asynchronous Bus Read AC characteristics, for details on when the output becomes valid.

Note that, since the Latch Enable input is transparent when set Low, VIL, Asynchronous Bus

Read operations can be performed when the memory is configured for Asynchronous Latch

Enable bus operations by holding Latch Enable Low, VIL throughout the bus operation.

M58BW16F Datasheet(PDF) 24 Page - STMicroelectronics

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