UPD78F0949 datasheet(3/72 Pages) RENESAS

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µPD78F0949

Overview of Functions

Major Changes

Page

Description

The internal high-speed RAM is 1024 x 8 bits

Note:

The mark 5 shows major revised points.

Part Number

Item

µPD78F0949

ROM

60 Kbytes

Internal high-speed RAM

1024 bytes

LCD Display RAM

40 bytes

Internal Expansion RAM

992 bytes

Internal

memory

EEPROM

256 bytes

Memory space

64 Kbytes

General registers

8 bits x 32 registers ( 8 bits x 8 registers x 4 banks)

Instruction cycle

On-chip instruction execution time selective function

When main system clock

selected

0,25 µs/0,5 µs/1 µs/2 µs/4 µs (at 8 MHz)

When subsystem clock

selected

122 µs (at 32.768 kHz)

Instruction set

•

16-bit operation

•

Multiplication/division ( 8 bits x 8 bits, 16 bits – 8 bits )

•

Bit manipulation ( set, reset, test, boolean operation )

•

BCD adjustment, etc.

Total

: 79

I/O ports

•

CMOS input

: 8

•

CMOS I/O

: 71

A/D converter

•

8 bit resolution x 8 channels

Serial Interface

•

3-wire mode : 1 channel

•

2-wire mode : 1 channel

•

UART mode : 1 channel

Timer

•

16 bit timer / event counter : 2 channels

•

8 bit timer / event counter : 2 channels

•

Watch timer

: 1 channel

•

Watchdog timer

: 1 channel

Timer output

3 ( 16-bit PWM output x 1, 8-bit PWM output x 2 )

Clock output

62,5 kHz, 125 kHz, 250 kHz, 500 kHz, 1 MHz, 2 MHz,

4 MHz, 8 MHz (at main system clock of 8.0 MHz)

CAN

1 channel

Maskable interrupts

Internal : 22

External : 5

Non-maskable interrupts

Internal : 1

Vectored

interrupts

Software interrupts

Internal : 1

Supply voltage

VDD = 4,0 V to 5,5 V

Package

100-pin plastic QFP ( 14 mm x 20 mm )

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