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UPD78F0949 Datasheet(PDF) 10 Page - Renesas Technology Corp

Part # UPD78F0949
Description  PRELIMINARY PRODUCT INFORMATION
PDF  72 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

UPD78F0949 Datasheet(HTML) 10 Page - Renesas Technology Corp

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µPD78F0949
3.2 Non-Port Pins
Table 3-2: Non-Port Pins (1/2)
Pin Name
I/O
Function
After
Reset
Alternate
Function Pin
INTP0
P00
INTP1
P01
INTP2
P02
INTP3
P03/T2P0
INTP4
Input
External interrupts with selectable valid edges (rising
edge, falling edge, both rising and falling edges)
Input
P04/TI01
SI0
P20
SI1
Input
Serial interface serial data input
Input
P23/SO1
SO0
P21
SO1
Output
Serial interface serial data output
Input
P23/SI1
SCK0
P22
SCK1
Input/
Output
Serial interface serial clock input / output
Input
P24
RxD
Input
Asynchronous serial interface data input
Input
P25
TxD
Output
Asynchronous serial interface data output
Input
P26
CRxD
Input
CAN serial data input
Input
-
CTxD
Output
CAN serial data output
Output
-
CCLK
Input
CAN serial clock input
-
CL1
TI00
P05/TO0
TI01
External count clock input to 16-bit timer (TM0)
P04/INTP4
TI20
Capture trigger input
P30
TI21
Capture trigger input
P31
TI22
Capture trigger input
P32
TI50
External count clock input to 8-bit timer (TM50)
P06/TO50
TI51
Input
External count clock input to 8-bit timer (TM51)
Input
P07/TO51
TO0
16-bit timer output
P05/TI00
T2P0
16-bit timer output
P03/INTP3
TO50
8-bit timer output (also used for PWM output)
P06/TI50
TO51
Output
8-bit timer output (also used for PWM output)
Input
P07/TI51
PCL
Output
Clock output (for main system clock trimming)
Input
P33/SGOA
AD0 to AD7
Input/
Output
Low-order address/data bus at external memory
expansion
Input
P40 to P47
A8 to A15
Output
High-order address/data bus at external memory
expansion
Input
P50 to P57
S39 to S32
RD
Strobe signal output for read operation from external
memory
P64
WR
Output
Strobe signal output for read operation from external
memory
Input
P65
ASTB
-
Strobe output externally latching address information
output to ports 4, 5 to access external memory
Input
P67
S0 to S7
P147 to P140
S8 to S15
P137 to P130
S16 to S23
P127 to P120
S24 to S31
P77 to P70
S32 to S39
Output
Segment signal output of LCD controller / driver
Input
P57 to P50
A15 to A8



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