VITESSE

SEMICONDUCTOR CORPORATION

Preliminary Datasheet

VSC7139

Quad Transceiver for

Gigabit Ethernet and Fibre Channel

G52196-0, Rev 3.3

Page 5

5/14/01

© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012

Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com

Internet: www.vitesse.com

Loopback Operation

Loopback operation is controlled by the PLUP (Parallel Loopback), SLPN (Serial Loopback) and LPNx

inputs as shown in Table 2. LPNx enables PLUP/SLPN on a per-channel basis when LOW. If LPNx is HIGH,

PLUP/SLPN have no impact on Channel x. When SLPN and PLUP are both HIGH the transmitter output is

held HIGH. When RXx is looped back to TXx, the data goes through a clock recovery unit so much of the input

jitter is removed. However, the TXx outputs may not meet jitter specifications listed in the “Transmitter AC

Specifications” due to low frequency jitter transfer from RXx to TXx.

Table 2: Loopback Selection

JTAG Access Port

A JTAG Access Port is provided to assist in board-level testing. Through this port most pins can be

accessed or controlled and all TTL outputs can be tri-stated. A full description of the JTAG functions on this

device is available in “VSC7139 JTAG Access Port Functionality.”

LPNx

PLUP

SLPN

Tranmitter Source

Receiver Source

LOW

LOW

LOW

Receiver

Receiver

LOW

LOW

HIGH

Transmitter

Receiver

LOW

HIGH

LOW

Transmitter

Transmitter

LOW

HIGH

HIGH

HIGH

Transmitter

HIGH

X

X

Transmitter

Receiver