MPQ8626 – 16V, 6A, HIGH EFFICIENCY SYNC, STEP-DOWN CONVERTER W/ ADJUSTABLE CURRENT LIMIT

MPQ8626 Rev. 1.1

www.MonolithicPower.com

19

8/16/2022

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PCB Layout Guidelines

Efficient

PCB

layout

is

critical

for

stable

operation. For the best performance, refer to

Figure 6 and follow the guidelines below.

1. Place the input MLCC capacitors as close

to VIN and PGND as possible.

2. Place the major MLCC capacitors on the

same layer as the MPQ8626.

3. Maximize the VIN and PGND copper plane

to minimize parasitic impedance.

4. Place as many PGND vias as possible as

close to PGND as possible to minimize both

parasitic impedance and thermal resistance.

5. Place the VCC decoupling capacitor close

to the device.

6. Connect AGND and PGND at the point of

the VCC capacitor's ground connection.

7. Place the BST capacitor as close to BST

and SW as possible.

8. Use traces with a width of 20mil or wider to

route the path.

9. Use a 0.1µF to 1µF bootstrap capacitor.

10. Place the REF capacitor close to TRK/REF

to AGND.

SW

VOUT

VIN

PGND

SW

MODE

BST

SW

VIN

PGND

CS

EN

TRK/REF

PGOOD

R1

R2

1

2

3

4

5

12

11

10

9

8

6

7

14

13

CFF

1

2

3

4

5

12

10

9

8

6

7

14

13

11

CREF

CVCC

VOUT

Figure 6: Example of PCB Layout (Placement & Top Layer PCB)

NOTE: Via size is 20/10mils.