MPQ8626 – 16V, 6A, HIGH EFFICIENCY SYNC, STEP-DOWN CONVERTER W/ ADJUSTABLE CURRENT LIMIT

MPQ8626 Rev. 1.1

www.MonolithicPower.com

11

8/16/2022

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PIN FUNCTIONS

PIN #

Name

Description

1, 14

PGND

System ground. PGND is the reference ground of the regulated output voltage.

PGND requires careful consideration during PCB layout. Connect PGND using wide

PCB traces.

2, 11

SW

Switch output. Connect SW to the inductor and bootstrap capacitor. SW is driven

up to VIN by the high-side switch during the on-time of the PWM duty cycle. The

inductor current drives SW low during the off-time. Connect SW using wide PCB

traces.

3

VIN

Input voltage. VIN supplies power to the internal MOSFET and regulator. Input

capacitors are needed to decouple the input rail. Connect VIN using wide PCB

traces.

4

CS

Current limit. Connect a resistor from CS to ground to set the current limit trip

point. See Table 2 for additional details.

5

EN

Enable. EN is an input signal that turns the regulator on or off. Drive EN high to turn

on the regulator; drive EN low to turn off the regulator. Connect EN to VIN through a

pull-up resistor or a resistive voltage divider for automatic start-up. Do not float EN.

6

FB

Feedback. An external resistor divider from the output to AGND tapped to FB sets

the output voltage. It is recommended to place the resistor divider as close to FB as

possible. Vias should be avoided on the FB traces.

7

AGND

Analog ground. Select AGND as the control circuit reference point.

8

TRK/REF

External tracking voltage input. The output voltage tracks this input signal.

Decouple TRK/REF with a ceramic capacitor placed as close to it as possible.

Ceramic capacitors with X7R or X5R grade dielectrics are recommended for their

stable temperature characteristics. The capacitance of this capacitor determines the

soft-start time. See Equation 2 and 3 for additional details.

9

PGOOD

Power good output. PGOOD is an open-drain signal. A pull-up resistor connected

to a DC voltage is required to indicate a logic high signal if the output voltage is

within regulation. There is a delay of about 1ms from the time FB is greater than or

equal to 92.5% and PGOOD pulling high.

10

BST

Bootstrap. Connect a capacitor between SW and BS to form a floating supply

across the high-side switch driver.

12

MODE

Operation mode selection. Program MODE to select CCM, pulse-skip mode, or

the operating switching frequency. See Table 1 for additional details.

13

VCC

Internal 3V LDO output. The driver and control circuits are powered from VCC.

Decouple VCC with a minimum 1µF ceramic capacitor as close to it as possible.

Ceramic capacitors with X7R or X5R grade dielectrics are recommended for their

stable temperature characteristics.