HT48R02 datasheet(14/38 Pages) HOLTEK

14 / 38 page

HT48R01/HT48R02/HT48R03

Rev. 1.00

December 20, 2006

²1² before entering the HALT mode, the wake-up func-

tion of the related interrupt will be disabled. Once a

wake-up event occurs, it takes 1024 tSYS (system clock

period) to resume normal operation. In other words, a

dummy period will be inserted after wake-up. If the

wake-up results from an interrupt acknowledgment, the

actual interrupt subroutine execution will be delayed by

one or more cycles. If the wake-up results in the next in-

struction execution, this will be executed immediately

after the dummy period is finished.

To minimise power consumption, all the I/O pins should

be carefully managed before entering the HALT status.

Reset

There are three ways in which a reset can occur:

· RES reset during normal operation

· RES reset during HALT

· WDT time-out reset during normal operation

The WDT time-out during HALT is different from other

chip reset conditions, since it can perform a

²warm re -

set

² that resets only the Program Counter and SP, leav-

ing the other circuits in their original state. Some regis-

ters remain unchanged during other reset conditions.

Most registers are reset to the

²initial condition² when

the reset conditions are met. By examining the PDF and

TO flags, the program can distinguish between different

²chip resets².

PDF

RESET Conditions

RES reset during power-up

RES reset during normal operation

RES wake-up HALT

WDT time-out during normal operation

WDT wake-up HALT

Note:

²u² means ²unchanged²

To guarantee that the system oscillator is started and

stabilised, the SST (System Start-up Timer) provides an

extra-delay of 1024 system clock pulses when the sys-

tem reset (power-up, WDT time-out or RES reset) or the

system awakes from the HALT state.

When a system reset occurs, the SST delay is added

during the reset period. Any wake-up from HALT will en-

able the SST delay.

An extra option load time delay is added during a system

reset (power-up, WDT time-out during normal mode or

RES reset).

The functional unit chip reset status are shown below.

Program Counter

000H

Interrupt

Disable

Prescaler

Clear

WDT

Clear. After master reset,

WDT begins counting

Timer/Event Counter

Off

Input/Output Ports

Input mode

Stack Pointer

Points to the top of the stack

R E S

V D D

1 0 0 k W

1 0 k W

0 . 1 m F *

0 . 0 1 m F *

Reset Circuit

Note:

²*² Make the length of the wiring, which is con-

nected to the RES pin as short as possible, to

avoid noise interference.

W a r m R e s e t

W D T

H A L T

C o l d

R e s e t

R E S

S y s t e m R e s e t

S S T

1 0 - b i t R i p p l e

C o u n t e r

O S C 1

Reset Configuration

t S S T

R E S

V D D

S S T T i m e - o u t

C h i p R e s e t

Reset Timing Chart

HT48R02 Datasheet(PDF) 14 Page - Holtek Semiconductor Inc

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