HT48R02 datasheet(17/38 Pages) HOLTEK

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HT48R01/HT48R02/HT48R03

Rev. 1.00

December 20, 2006

Bit No.

Label

Function

0~2

T0PSC0~

T0PSC2

To define the prescaler stages, T0PSC2, T0PSC1, T0PSC0=

000: fINT=fTP

001: fINT=fTP/2

010: fINT=fTP/4

011: fINT=fTP/8

100: fINT=fTP/16

101: fINT=fTP/32

110: fINT=fTP/64

111: fINT=fTP/128

T0E

To define the TMR active edge of the timer/event counter

In event counter mode (T0M1,T0M0)=(0,1):

1: count on falling edge

0: count on rising edge

In pulse width measurement mode (T0M1,T0M0)=(1,1):

1: start counting on rising edge, stop on falling edge

0: start counting on falling edge, stop on rising edge

T0ON

To enable or disable timer counting (0=disabled; 1=enabled)

T0S

Timer clock source selection

0: fSYS

1: RTC

T0M0

T0M1

To define the operating mode (T0M1, T0M0)

01=Event count mode (external clock)

10=Timer mode (internal clock)

11=Pulse width measurement mode

00=Unused

TMR0C (0EH) Register

In the case of timer/event counter OFF condition, writing

data to the timer/event counter preload register will also

reload that data to the timer/event counter. But if the

timer/event counter is turned on, data written to it will

only be kept in the timer/event counter preload register.

The timer/event counter will still operate until overflow

occurs. When the timer/event counter is read, the clock

will be blocked to avoid errors. As clock blocking may re-

sults in a counting error, this must be taken into consid-

eration by the programmer.

The bit 0~2 of the TMR0C can be used to define the

pre-scaling stages of the internal clock sources of the

timer/event counter. The definitions are as shown. The

timer/event counter overflow signals can be used to

generate signals for the buzzer.

Bit No.

Label

Function

0~2

Unused bit, read as

²0²

T1E

To define the TMR active edge of the timer/event counter

In event counter mode (T1M1,T1M0)=(0,1):

1: count on falling edge

0: count on rising edge

In pulse width measurement mode (T1M1,T1M0)=(1,1):

1: start counting on rising edge, stop on falling edge

0: start counting on falling edge, stop on rising edge

T1ON

To enable or disable timer counting (0=disabled; 1=enabled)

T1S

Timer clock source selection

0: fSYS/4

1: RTC

T1M0

T1M1

To define the operating mode (T1M1, T1M0)

01=Event count mode (external clock)

10=Timer mode (internal clock)

11=Pulse width measurement mode

00=Unused

TMR1C (11H) Register

HT48R02 Datasheet(PDF) 17 Page - Holtek Semiconductor Inc

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