HT48R02 datasheet(18/38 Pages) HOLTEK

18 / 38 page

HT48R01/HT48R02/HT48R03

Rev. 1.00

December 20, 2006

Input/Output Ports

There are 7 bi-directional input/output lines and 1 input

line in the microcontroller, labeled as PA, which are

mapped to the data memory of [12H]. All of the I/O ports

can be used for input or output operations. For input op-

eration, these ports are non-latching, that is, the inputs

must be ready at the T2 rising edge of instruction

²MOV

A,[m]

² (m=12H). For output operation, all the data is

latched and remains unchanged until the output latch is

rewritten. Each I/O line has its own control register

(PAC) to control the input/output configuration (PA7 for

input only). With this control register, a CMOS output or

Schmitt trigger input ( with or without pull-high resistor

structures) can be reconfigured dynamically (i.e.

on-the-fly) under software control ( the PA7 only provide

input mode). To function as an input, the corresponding

latch of the control register must write

²1². The input

source also depends on the control register. If the con-

trol register bit is

²1², the input will read the pad state. If

the control register bit is

²0², the contents of the latches

will move to the internal bus. The latter is possible in the

²read-modify-write² instruction. For output function,

CMOS is the only configuration. These control register

is mapped to locations 13H. After a chip reset, these in-

put/output lines remain at high levels or floating state

(dependent on pull-high options). Each bit of these in-

put/output latches can be set or cleared by

²SET [m].i²

and ²CLR [m].i² (m=12H) instructions. Some instruc-

tions first input data and then follow the output opera-

tions. For example,

²SET [m].i², ²CLR [m].i², ²CPL [m]²,

²CPLA [m]² read the entire port states into the CPU, ex-

ecute the defined operations (bit-operation), and then

write the results back to the latches or the accumulator.

· Wake up and pull-high function

Each line (except PA7) of PA port supports waking-up

MCU and pull-high function which are controlled by

PAWK, PAPU registers respectively. PA7 hasn

¢t

wake-up and pull-high function.

Bit No.

Label

Function

0~6

PAWK0~

PAWK6

PAWKn= 0, PAn wake-up is dis-

able

PAWKn=1, PAn wake-up is en-

able

Unused bit, read as

²0²

PAWK (15H) Register

Bit No.

Label

Function

0~6

PAPU0~

PAPU6

PAPUn= 0, PAn pull-up is disable

PAPUn=1, PAn pull-up is enable

Unused bit, read as

²0²

PAPU (14H) Register

V D D

B Z E N ( P A 0 / P A 1 )

C o n t r o l B i t

D a t a B u s

W r i t e C o n t r o l R e g i s t e r

C h i p R e s e t

R e a d C o n t r o l R e g i s t e r

W r i t e D a t a R e g i s t e r

D a t a B i t

C K

P A 0 / B Z

P A 1 / B Z

P A 2 / T M R 0

P A 3 / I N T

P A 4 / T M R 1

P A 5 / O S C 2

P A 6 / O S C 1

T M R f o r P A 2 o n l y

I N T f o r P A 3 o n l y

S y s t e m W a k e - u p ( P A 0 ~ P A 6 o n l y )

R e a d D a t a R e g i s t e r

( P A 1 , P A 0 )

( B Z , B Z )

P A W K 6 ~ P A W K 0

P A P U 6 ~ P A P U 0

Input/Output Ports (PA0~PA6)

R e a d D a t a

D a t a B u s

R E S f o r P A 7 o n l y

P A 7

Input/Output Ports (PA7)

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