TAS5036AIPFC datasheet(31/62 Pages) TI

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Serial Control Interface Register Definitions

SLES061B—November 2002—Revised January 2004

TAS5036A

Serial Control Interface Register Definitions

Table 3−1 shows the register map for the TAS5036A. Default values in this section are in bold.

Table 3−1. I2C Register Map

ADDR HEX

DESCRIPTION

General status register

Error status register

System control register 0

System control register 1

Error recovery register

Automute delay

DC-offset control register channel 1

DC-offset control register channel 2

DC-offset control register channel 3

DC-offset control register channel 4

DC-offset control register channel 5

DC-offset control register channel 6

Interchannel delay register channel 1

Interchannel delay register channel 2

Interchannel delay register channel 3

Interchannel delay register channel 4

Interchannel delay register channel 5

Interchannel delay register channel 6

ABD delay register

Volume control register channel 1

Volume control register channel 2

Volume control register channel 3

Volume control register channel 4

Volume control register channel 5

Volume control register channel 6

Individual channel mute

The volume table is contained in Appendix A.

Default values are shown in bold in the following tables.

3.1

General Status Register (0x00)

Table 3−2. General Status Register (Read Only)

FUNCTION

No volume update is in progress.

Volume update is in progress.

Always 0

Device identification code

Any valid signal is inactive (see status register, 0x03) (see Note 1).

No internal errors (all valid signals are high)

NOTE 1: This bit is reset automatically when one or more channels are active.

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