RT5133

R

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DS5133-02

February

2021

18

I

2C Interface

The following table shows the RT5133 unique address to AP, respectively.

Slave Address

MSB

LSB

R/W Bit

R/W

001100

0

1/0

31/30

The I2C interface bus must be connect a resistor 2.2k

 to power node and independent connection to processor,

individually. The I2C interface also supports High-Speed (HS) mode for data transfer rate up to 3.4Mbits. The I2C

timing diagrams are listed below.

S

0

1

A

P

LSB

MSB

A

Assume Address = m

Data for Address = m

Data for Address = m + N - 1

A

Data for Address = m + 1

S

0

P

Assume Address = m

Data for Address = m

Data for Address = m + N - 1

Data for Address = m + 1

Sr

Slave Address

Register Address

Slave Address

Data 1

R/W

R/W

Data N

LSB

MSB

A

A

A

A

A

A

A

A

Read N bytes of data from Registers

LSB

MSB

Data 2

Data N

LSB

MSB

LSB

Slave Address

Register Address

Data 1

Data 2

MSB

MSB

LSB

Write N bytes of data to Registers

Driven by Master,

Driven by Slave,

Start,

Repeat Start

Stop,

S

Sr

P

S

0

1

A

P

LSB

MSB

Assume Address = m

Data for Address = m

Sr

Slave Address

Register Address

Slave Address

Data

R/W

A

A

A

Read single byte of data from Register

S

0

P

Assume Address = m

Data for Address = m

R/W

A

A

A

Slave Address

Register Address

Data

MSB

LSB

Write single byte of data to Register

Figure 5. I2C Timing Diagrams

SDA

SCL

tF

tLOW

tHD;STA

tHD;DAT

tHIGH

tSU;DAT

tSU;STA

tHD;STA

tSP

tBUF

tSU;STO

P

S

tR

Sr

S

tF

tR

Figure 6. I2C Waveform Information