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RT6310C/CH Datasheet(PDF) 45 Page - Richtek Technology Corporation

Part # RT6310C/CH
Description  10A, 23V Synchronous Step-Down Converter with 3.3V/5V LDO
PDF  54 Pages
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Manufacturer  RICHTEK [Richtek Technology Corporation]
Direct Link  http://www.richtek.com
Logo RICHTEK - Richtek Technology Corporation

RT6310C/CH Datasheet(HTML) 45 Page - Richtek Technology Corporation

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RT6310
Copyright © 2023 Richtek Technology Corporation. All rights reserved.
is a registered trademark of Richtek Technology Corporation.
DS6310-04
August 2023
www.richtek.com
45
RT6310A/AH/D/DH
10
11
12
13
14
15
16
17
18
19
20
21
22
23
1
2
3
4
5
6
7
8
9
LX
LX
BOOT
PGND
VIN
VIN
EN/MODE
L
CIN
CIN
COUT
CBOOT
RBOOT
COUT
COUT
COUT
RFB1
RFB2
CFF
GND
VOUT
GND
CIN
GND
VCC_EXT
VEN/MODE
LX pin:
LX should be connected to
inductor by wide and short trace,
and Do NOT use any via for LX.
Keep sensitive components
away from this area.
PGND pin:
For thermal performance, the vias
under the IC must be placed through
at least two layers of PGND trace.
The recommended via size is 8 mil
drill/16 mil copper width.
GND
CIN:
The input capacitor must be
placed as close to the IC as
possible for noise immunity
and phase ring.
VIN pin:
The VIN trace should be wide
enough for high current density
application (at least two VIN
layers). The number of vias is
based on input maximum current
to design.
VIN
AGND pin:
The AGND and PGND should be
connected by single point grounding to
avoid ground level shift.
CFF:
The optional compensation components
(CFF) must be connected as close to the
IC as possible.
GND
Figure 21. RT6310A/AH/D/DH Layout Guide
RT6310B/BH
L
CIN
CIN
COUT
CBO OT
RBO OT
COUT
COUT
COUT
CLDO
GND
VOUT
GND
CIN
GND
VEN/MODE
LX pin:
LX should be connected to
inductor by wide and short trace,
and Do NOT use any via for LX.
Keep sensitive components
away from this area.
PGND pin:
For thermal performance, the vias
under the IC must be placed through
at least two layers of PGND trace.
The recommended via size is 8 mil
drill/16 mil copper width.
GND
CIN:
The input capacitor must be
placed as close to the IC as
possible for noise immunity
and phase ring.
VIN pin:
The VIN trace should be wide
enough for high current density
application (at least two VIN
layers). The number of vias is
based on input maximum current
to design.
VIN
AGND pin:
The AGND and PGND should be
connected by single point grounding to
avoid ground level shift.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
1
2
3
4
5
6
7
8
9
LX
LX
BOOT
PGND
VIN
VIN
EN/MODE
CEXT
VCC_EXT
GND
GND
Figure 22. RT6310B/BH Layout Guide



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