www.ti.com

Mute Timing (MUTE)

VOLUME

MUTE

Normal

Operation

M-State

Normal

Operation

T0032-01

SERIAL INTERFACE CONTROL AND TIMING

TAS5086

SLES131A – FEBRRUARY 2005 – REVISED MAY 2006

Control-signal parameters over recommended operating conditions (unless otherwise noted)

Control-signal parameters over recommended operating conditions (unless otherwise noted)

PARAMETER

MIN

TYP

MAX

UNIT

Defined by rate setting(1)

ms

(1)

See the Volume Control Register (0x0E) section.

Figure 7. Mute Timing

used to clock in the data. A delay of one bit clock occurs from the time the LRCLK signal changes state to the

first bit of data on the data lines. The data is written MSB first and is valid on the rising edge of bit clock. The

TAS5086 masks unused trailing data bit positions.

13

Submit Documentation Feedback