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TAS5086DBT Datasheet(PDF) 21 Page - Texas Instruments |
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TAS5086DBT Datasheet(HTML) 21 Page - Texas Instruments |
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21 / 41 page  www.ti.com A6 A0 ACK Acknowledge I2C Device Address and Read/Write Bit R/W A6 A0 R/W ACK A0 ACK D7 D0 ACK Start Condition Stop Condition Acknowledge Acknowledge Acknowledge Last Data Byte ACK First Data Byte Repeat Start Condition Not Acknowledge I2C Device Address and Read/Write Bit Subaddress Other Data Bytes A7 A6 A5 D7 D0 ACK Acknowledge D7 D0 T0036-04 COMMAND CHARACTERISTICS SERIAL CONTROL INTERFACE REGISTER SUMMARY TAS5086 SLES131A – FEBRRUARY 2005 – REVISED MAY 2006 I2C SERIAL CONTROL INTERFACE (continued) Figure 18. Multiple-Byte Read Transfer The TAS5086 has two groups of I2C commands. One set is commands that are designed specifically to be operated while audio is streaming and that have built-in mechanisms to prevent noise, clicks, and pops. The other set does not have this built-in protection. Commands that are designed to be adjusted while audio is streaming • Master volume • Master mute • Individual channel volume • Individual channel mute Commands that the system executes without additional processing to prevent noise, clicks, or pops (in a number of cases this does not produce an audible click and pop) • Serial data interface format • De-emphasis • Sample rate conversion • Input multiplexer • Output multiplexer • Biquads • Downmix • Channel delay • Enable/disable automatic MCLK and data-rate detection • Manual or automatic MCLK and data-rate setting • Enable/disable dc blocking • Hard/soft unmute from clock error NO. OF SUBADDRESS REGISTER NAME CONTENTS INITIALIZATION VALUE BYTES A u indicates unused bits 0x00 Clock control register 1 Description shown in subsequent section 6C 0x01 Device ID register 1 Description shown in subsequent section 03 0x02 Error status register 1 Description shown in subsequent section 00 0x03 System control register 1 1 Description shown in subsequent section A0 0x04 Serial data interface register 1 Description shown in subsequent section 05 0x05 System control register 2 1 Description shown in subsequent section 60 0x06 Softmute register 1 Description shown in subsequent section 00 0x07 Master volume 1 Description shown in subsequent section FF (mute) 21 Submit Documentation Feedback |
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