TAS5086DBT datasheet(19/41 Pages) TI

19 / 41 page

www.ti.com

SINGLE-BYTE WRITE

R/W ACK A7

ACK

Start

Condition

Stop

Condition

Acknowledge

I2C Device Address and

Read/Write Bit

Subaddress

Data Byte

T0036-01

MULTIPLE-BYTE WRITE AND INCREMENTAL MULTIPLE-BYTE WRITE

D0 ACK

Stop

Condition

Acknowledge

I2C Device Address and

Read/Write Bit

Subaddress

Last Data Byte

R/W ACK A7

ACK D7

ACK

Start

Condition

Acknowledge

First Data Byte

Other Data Bytes

ACK

Acknowledge

T0036-02

TAS5086

SLES131A – FEBRRUARY 2005 – REVISED MAY 2006

I2C SERIAL CONTROL INTERFACE (continued)

During multiple-byte write operations, the TAS5086 compares the number of bytes transmitted to the number of

bytes that are required for each specific subaddress. If a write command is received for a biquad subaddress,

the TAS5086 expects to receive five 32-bit words. If fewer than five 32-bit data words have been received when

a stop command (or another start command) is received, the data received is discarded. Similarly, if a write

command is received for a mixer coefficient, the TAS5086 expects to receive one 32-bit word.

Supplying a subaddress for each subaddress transaction is referred to as random I2C addressing. The TAS5086

also supports sequential I2C addressing. For write transactions, if a subaddress is issued, followed by data for

that subaddress and the 15 subaddresses that follow, a sequential I2C write transaction has taken place, and the

data for all 16 subaddresses is successfully received by the TAS5086. For I2C sequential write transactions, the

subaddress then serves as the start address and the amount of data subsequently transmitted, before a stop or

start is transmitted, determines how many subaddresses are written. As was true for random addressing,

sequential addressing requires that a complete set of data be transmitted. If only a partial set of data is written to

the last subaddress, the data for the last subaddress is discarded. However, all other data written is accepted;

just the incomplete data is discarded.

As shown is Figure 15, a single-byte data write transfer begins with the master device transmitting a start

condition, followed by the I2C device address and the read/write bit. The read/write bit determines the direction

of the data transfer. For a write data transfer, the read/write bit must be set to 0. After receiving the correct I2C

device address and the read/write bit, the TAS5086 device responds with an acknowledge bit. Next, the master

transmits the address byte or bytes corresponding to the TAS5086 internal memory address being accessed.

After receiving the address byte, the TAS5086 again responds with an acknowledge bit. Next, the master device

transmits the data byte to be written to the memory address being accessed. After receiving the data byte, the

TAS5086 again responds with an acknowledge bit. Finally, the master device transmits a stop condition to

complete the single-byte data write transfer.

Figure 15. Single-Byte Write Transfer

A multiple-byte data write transfer is identical to a single-byte data write transfer, except that multiple data bytes

are transmitted by the master device to TAS5086 as shown in Figure 16. After receiving each data byte, the

TAS5086 responds with an acknowledge bit.

Figure 16. Multiple-Byte Write Transfer

The I2C supports a special mode that permits I2C write operations to be broken up into multiple data write

operations that are multiples of 4 data bytes. These are 6-, 10-, 12-, 16-, ..., etc., -byte write operations that are

composed of a device address, read/write bit, and subaddress and any multiple of 4 bytes of data. This permits

the system to write large register values incrementally without blocking other I2C transactions.

Submit Documentation Feedback

TAS5086DBT Datasheet(PDF) 19 Page - Texas Instruments

TAS5086DBT Datasheet(HTML) 19 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41

Datasheet Download

Link URL