M25PE40VMP6P datasheet(26/60 Pages) STMICROELECTRONICS

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Instructions

M25PE40

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6.5

Write Status Register (WRSR)

The Write Status Register (WRSR) instruction allows new values to be written to the Status

Note:

The Status Register BPi and SRWD bits are available in the in the T9HX process only. See

Important note on page 6 for more details.

Before the Write Status Register (WRSR) instruction can be accepted, a Write Enable

(WREN) instruction must previously have been executed. After the Write Enable (WREN)

instruction has been decoded and executed, the device sets the Write Enable Latch (WEL).

The Write Status Register (WRSR) instruction is entered by driving Chip Select (S) Low,

followed by the instruction code and the data byte on Serial Data Input (D).

The instruction sequence is shown in Figure 11.

The Write Status Register (WRSR) instruction has no effect on b6, b5, b1 and b0 of the

Status Register. b6 and b5 are always read as 0.

Chip Select (S) must be driven High after the eighth bit of the data byte has been latched in.

If not, the Write Status Register (WRSR) instruction is not executed. As soon as Chip Select

(S) is driven High, the self-timed Write Status Register cycle (whose duration is tW) is

initiated. While the Write Status Register cycle is in progress, the Status Register may still

be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP)

bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed.

When the cycle is completed, the Write Enable Latch (WEL) is reset.

The Write Status Register (WRSR) instruction allows the user to change the values of the

Block Protect (BP2, BP1, BP0) bits, to define the size of the area that is to be treated as

read-only, as defined in Table 3. The Write Status Register (WRSR) instruction also allows

the user to set or reset the Status Register Write Disable (SRWD) bit in accordance with the

Write Protect (W) signal (see Section 6.4.4).

If a Write Status Register (WRSR) instruction is interrupted by a Reset Low pulse, the

internal cycle of the Write Status Register operation (whose duration is tW) is first completed

(provided that the supply voltage VCC remains within the operating range). After that the

device enters the Reset mode (see also Table 12: Device status after a Reset Low pulse

and Table 22: Timings after a Reset Low pulse).

Figure 11.

Write Status Register (WRSR) instruction sequence

AI02282D

3456789 10 11 12 13 14 15

High Impedance

Instruction

Status

765432

MSB

M25PE40VMP6P Datasheet(PDF) 26 Page - STMicroelectronics

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