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PSD835G2-90UT Datasheet(PDF) 1 Page - STMicroelectronics |
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PSD835G2-90UT Datasheet(HTML) 1 Page - STMicroelectronics |
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1 / 102 page ![]() 1/102 March 2004 PSD835G2 Flash PSD, 5V Supply, for 8-bit MCUs 4 Mbit + 256 Kbit Dual Flash Memories and 64 Kbit SRAM FEATURES SUMMARY ■ FLASH IN-SYSTEM PROGRAMMABLE (ISP) PERIPHERAL FOR 8-BIT MCUS ■ DUAL BANK FLASH MEMORIES – 4 Mbits of Primary Flash Memory (8 uniform sectors, 64Kbyte) – 256 Kbits of Secondary Flash Memory with 4 sectors – Concurrent operation: READ from one memory while erasing and writing the other ■ 64 KBIT OF BATTERY-BACKED SRAM ■ 52 RECONFIGURABLE I/O PORTS ■ ENHANCED JTAG SERIAL PORT ■ PLD WITH MACROCELLS – Over 3000 Gates of PLD: CPLD and DPLD – CPLD with 16 Output Macrocells (OMCs) and 24 Input Macrocells (IMCs) – DPLD - user defined internal chip select decoding ■ 52 INDIVIDUALLY CONFIGURABLE I/O PORT PINS They can be used for the following functions: – MCU I/Os –PLD I/Os – Latched MCU address output – Special function I/Os. – I/O ports may be configured as open-drain outputs. ■ IN-SYSTEM PROGRAMMING (ISP) WITH JTAG – Built-in JTAG compliant serial port allows full-chip In-System Programmability – Efficient manufacturing allow easy product testing and programming – Use low cost FlashLINK cable with PC ■ PAGE REGISTER – Internal page register that can be used to expand the microcontroller address space by a factor of 256 ■ PROGRAMMABLE POWER MANAGEMENT Figure 1. Package ■ HIGH ENDURANCE: – 100,000 Erase/WRITE Cycles of Flash Memory – 1,000 Erase/WRITE Cycles of PLD – 15 Year Data Retention ■ 5V±10% SINGLE SUPPLY VOLTAGE ■ STANDBY CURRENT AS LOW AS 50µA ■ MEMORY SPEED – 70ns Flash memory and SRAM access time for VCC = 4.5V to 5.5V – 90ns Flash memory and SRAM access time for VCC = 4.5V to 5.5V TQFP80 (U) |
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